Binary translation mechanism

Patent metadata

Field	Value
Publication number	US-9665374-B2
Application number	US-201414574797-A
Country	US
Kind code	B2
Filing date	Dec 18, 2014
Priority date	Dec 18, 2014
Publication date	May 30, 2017
Grant date	May 30, 2017

Abstract

A method is described. The method includes receiving an instruction, accessing a return cache to load a predicted return target address upon determining that the instruction is a return instruction, searching a lookup table for executable binary code upon determining that the predicted translated return target address is incorrect and executing the executable binary code to perform a binary translation.

First claim

What is claimed is:

1. A binary translation device comprising:
a memory module to maintain a hierarchical structural organization, including:
a cache; and
a lookup table;

a binary translation module to translate instructions into executable binary code and perform return address prediction of a return instruction by searching the cache for a predicted translated return target address and searching the lookup table for executable binary code upon determining that the predicted translated return target address is incorrect, wherein the binary translation module further to translate the return instruction to a code sequence that retrieves the predicted translated return target address by indexing the cache and performing an indirect control transfer at the predicted translated return address; and
a processing module to execute the executable binary code.

2. The device of claim 1 , further comprising a return address buffer, wherein the binary translation module to search the return address buffer for the predicted translated return target address prior to performing translation of a leaf instruction.

3. The device of claim 1 , wherein the cache comprises buckets including a single field to store the predicted translated return target address.

4. The device of claim 3 , wherein an entry is added to the cache by the binary translator module to store the predicted translated return address in response to receiving a call instruction.

5. The device of claim 4 , wherein the predicted translated return target address is stored to the return cache by translating the call instruction to a code sequence that chooses a return cache bucket based on a hash of a guest return address.

6. The device of claim 5 , wherein the lookup table is searched to determine whether there is a match for the guest return target address.

7. The device of claim 6 , wherein the lookup table is a direct map look-up table indexed by a hash of a return target address.

8. The device of claim 7 , wherein the lookup table comprises buckets including the guest return target address and translation code mapped to the return target address.

9. The device of claim 8 , wherein the lookup table is filled by the binary translator module performing a slow look-up path when there is a miss in the lookup table.

10. At least one non-transitory computer readable medium, which when executed by a processor, cause the processor to perform operations comprising:
receiving an instruction;
determining whether the instruction is a return instruction;
determining whether the return instruction is a leaf instruction upon determining that the instruction is a return instruction;
accessing a return address buffer to load the predicted return target address upon determining that the instruction is a leaf instruction;
searching a lookup table for executable binary code upon determining that the predicted return target address is incorrect; and
executing the executable binary code to perform a binary translation.

11. The at least one computer readable medium of claim 10 , which when executed by a processor, cause the processor to further perform jumping to a predicted target translation upon determining that the predicted return target address is correct.

12. At least one non-transitory computer readable medium, which when executed by a processor, cause the processor to perform operations comprising:
receiving an instruction;
accessing a return cache to load a predicted return target address upon determining that the instruction is a return instruction;
searching a lookup table for executable binary code upon determining that the predicted return target address is incorrect;
executing the executable binary code to perform a binary translation; and
storing the predicted return target address in the return cache upon determining that the instruction is a call instruction.

13. The at least one computer readable medium of claim 12 , which when executed by a processor, cause the processor to further perform:
determining whether the call instruction is a leaf instruction; and
loading the address of the call instruction into a return address buffer upon determining that the call instruction is a leaf instruction.

14. The at least one computer readable medium of claim 12 wherein the predicted return target address is stored in the return cache by translating the call instruction to a code sequence that chooses a return cache bucket based on a hash of a guest return address.

15. The at least one computer readable medium of claim 14 , which when executed by a processor, cause the processor to further perform determining whether the lookup table has an entry corresponding to the guest return address.

16. The at least one computer readable medium of claim 15 , which when executed by a processor, cause the processor to further perform jumping to a predicted target translation upon determining that the lookup table has an entry corresponding to the guest return address.

17. The at least one computer readable medium of claim 15 , which when executed by a processor, cause the processor to further perform filling an entry in the lookup table upon determining that the lookup table does not have an entry corresponding to the guest return address.

18. The at least one computer readable medium of claim 17 , wherein the lookup table is filled by performing a slow look-up path.

19. A binary translation method comprising:
receiving an instruction;
determining whether the instruction is a return instruction;
determining whether the return instruction is a leaf instruction upon determining that the instruction is a return instruction;
accessing a return address buffer to load the predicted return target address upon determining that the instruction is a leaf instruction;
searching a lookup table for executable binary code upon determining that the predicted return target address is incorrect; and
executing the executable binary code to perform a binary translation.

20. The method of claim 19 , further comprising jumping to a predicted target translation upon determining that the predicted return target address is correct.

21. The method of claim 19 , further comprising storing the predicted return target address in the return cache upon determining that the instruction is a call instruction.

22. The method of claim 21 , further comprising:
determining whether the call instruction is a leaf instruction; and
loading the address of the call instruction into a return address buffer upon determining that the instruction is a leaf instruction.

Assignees

• Yamada Koichi
• Bijlani Ashish
• Lu Jiwei
• Zhao cheng yan
• Intel Corp

Inventors

• Yamada Koichi
• Bijlani Ashish
• Lu Jiwei
• Zhao cheng yan

Classifications

• G06F9/30145 Primary

  Instruction analysis, e.g. decoding, instruction word fields · CPC title

• G06F9/3806 Primary

  using address prediction, e.g. return stack, branch history buffer · CPC title

• G06F8/52 Primary

  Binary to binary · CPC title

• G06F9/323

  for indirect branch instructions · CPC title

• G06F9/30054

  Unconditional branch instructions · CPC title