Method and apparatus for virtualization

Patent metadata

Field	Value
Publication number	US-9665300-B2
Application number	US-201615192214-A
Country	US
Kind code	B2
Filing date	Jun 24, 2016
Priority date	Apr 28, 2010
Publication date	May 30, 2017
Grant date	May 30, 2017

Abstract

A virtual system on chip (VSoC) is an implementation of a machine that allows for sharing of underlying physical machine resources between different virtual systems. A method or corresponding apparatus of the present invention relates to a device that includes a plurality of virtual systems on chip and a configuring unit. The configuring unit is arranged to configure resources on the device for the plurality of virtual systems on chip as a function of an identification tag assigned to each virtual system on chip.

First claim

What is claimed is:

1. A device comprising:
a plurality of virtual systems on chip, each virtual system on chip (VSoC) relating to a subset of a plurality of resources on a single physical chip;
a plurality of access control elements on the single physical chip; and
a configuring unit on the single physical chip, the configuring unit arranged to:
assign memory subsets of a given memory to each of the plurality of virtual systems on chip; and
set each access control element to control whether a given VSoC of the plurality of virtual systems on chip is enabled to access a given at least one location of the given memory, wherein a granularity of memory protection provided is based on a programmed memory size of the given memory and a total element number of the plurality of access control elements.

2. The device of claim 1 , wherein the configuring unit is further arranged to:
assign a unique identification tag of a plurality of identification tags to each VSoC;
assign each memory subset a given identification tag of the plurality of identification tags, the given identification tag assigned to a corresponding VSoC to which the memory subset is assigned; and
provide the granularity of memory protection further based on a number of the plurality of identification tags assigned.

3. The device of claim 1 , wherein:
the total element number of the plurality of access control elements is static;
the programmed memory size of the given memory is variable.

4. The device of claim 2 , wherein the number of the plurality of identification tags assigned is variable.

5. The device of claim 1 , wherein the given memory is a Dynamic Random Access Memory (DRAM) and the DRAM is shared by each VSoC of the plurality of virtual systems on chip.

6. The device of claim 1 , wherein the given memory is a level two cache and the level two cache is shared by each VSoC of the plurality of virtual systems on chip.

7. The device of claim 6 , wherein the configuring unit is further arranged to:
assign a unique identification tag of a plurality of identification tags to each VSoC;
assign each memory subset a given identification tag of the plurality of identification tags, the given identification tag assigned to a corresponding VSoC to which the memory subset is assigned; and
wherein the level two cache is configured to enable or restrict access to at least one other memory by the plurality of virtual systems on chip based on a first identification tag of the plurality of identification tags associated with the access and a second identification tag assigned to the at least one other memory.

8. The device of claim 1 , wherein at least one exclusive partition of the given memory is assigned to each VSoC of the plurality of virtual systems on chip.

9. The device of claim 8 , wherein the configuring unit is further arranged to:
assign a unique identification tag of a plurality of identification tags to each VSoC;
assign each memory subset a given identification tag of the plurality of identification tags, the given identification tag assigned to a corresponding VSoC to which the memory subset is assigned; and
wherein a first number of the at least one exclusive partition assigned is based on a second number of the plurality of identification tags assigned and a corresponding level of quality of service associated with each VSoC of the plurality of virtual systems on chip.

10. The device of claim 1 , wherein each VSoC of the plurality of virtual systems on chip serves as a virtualized execution environment for executing operating systems and embedded applications.

11. A method comprising:
storing a plurality of access control elements on a single physical chip;
assigning memory subsets of a given memory to each of a plurality of virtual systems on chip, each virtual system on chip (VSoC) relating to a subset of a plurality of resources on the single physical chip; and
setting each access control element to control whether a given VSoC of the plurality of virtual systems on chip is enabled to access a given at least one location of the given memory; and
providing a granularity of memory protection based on a programmed memory size of the given memory and a total element number of the plurality of access control elements set.

12. The method of claim 11 , further comprising:
assigning a unique identification tag of a plurality of identification tags to each VSoC;
assigning each memory subset a given identification tag of the plurality of identification tags, the given identification tag assigned to a corresponding VSoC to which the memory subset is assigned; and
providing the granularity of memory protection is further based on a number of the plurality of identification tags assigned.

13. The method of claim 11 , wherein:
the total element number of the plurality of access control elements is static;
the programmed memory size of the given memory is variable.

14. The method of claim 12 , wherein the number of the plurality of identification tags assigned is variable.

15. The method of claim 11 , wherein the given memory is a Dynamic Random Access Memory (DRAM) shared by each VSoC of the plurality of virtual systems on chip.

16. The method of claim 11 , wherein the given memory is a level two cache shared by each VSoC of the plurality of virtual systems on chip.

17. The method of claim 16 , further including:
assigning a unique identification tag of a plurality of identification tags to each VSoC;
assigning each memory subset a given identification tag of the plurality of identification tags, the given identification tag assigned to a corresponding VSoC to which the memory subset is assigned; and
configuring the level two cache to enable or restrict access to at least one other memory by the plurality of virtual systems on chip based on a first identification tag of the plurality of identification tags associated with the access and a second identification tag assigned to the at least one other memory.

18. The method of claim 11 , further comprising assigning at least one exclusive partition of the given memory to each VSoC of the plurality of virtual systems on chip.

19. The method of claim 18 , further including:
assigning a unique identification tag of a plurality of identification tags to each VSoC;
assigning each memory subset a given identification tag of the plurality of identification tags, the given identification tag assigned to a corresponding VSoC to which the memory subset is assigned; and
assigning a first number of the at least one exclusive partition based on a second number of the plurality of identification tags assigned and a corresponding level of quality of service associated with each VSoC of the plurality of virtual systems on chip.

20. The method of claim 11 , further including configuring each VSoC of the plurality of virtual systems on chip to serve as a virtualized execution environment for executing operating systems and embedded applications.

Assignees

• Cavium Inc

Inventors

• Hussain Muhammad Raghib
• Goyal Rajan
• Kessler Richard

Classifications

• G06F12/14

  Protection against unauthorised use of memory {or access to memory} · CPC title

• G06F9/45558

  Hypervisor-specific management and integration aspects · CPC title

• G06F3/0637 Primary

  Permissions · CPC title

• G06F2212/1008

  Correctness of operation, e.g. memory ordering · CPC title

• G06F3/0664

  at device level, e.g. emulation of a storage device or system · CPC title