Position indicator and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-9665190-B2
Application number	US-201514810202-A
Country	US
Kind code	B2
Filing date	Jul 27, 2015
Priority date	Aug 4, 2014
Publication date	May 30, 2017
Grant date	May 30, 2017

Abstract

A position indicator includes: a chassis; a substrate disposed inside the chassis; a coil; capacitors disposed on the substrate; interconnects disposed on the substrate such that each at least partially connects a respective one of the capacitors to the coil in parallel; and pairs of land patterns. Each pair of land patterns includes a first land pattern and a second land pattern. Each of the interconnects has a first end connected to a first end of the coil and a second end connected to a second end of the coil, and is connected to one of the capacitors. The pairs of land patterns are disposed such that each of the interconnects is at least partially interposed between the first land pattern and the second land pattern of one of the pairs of land patterns.

First claim

What is claimed is:

1. A position indicator comprising:
a chassis;
a substrate disposed inside of the chassis;
a coil;
a plurality of capacitors disposed on the substrate;
a plurality of interconnects disposed on the substrate such that each of the plurality of interconnects at least partially connects a respective one of the plurality of capacitors to the coil in parallel; and
a plurality of pairs of land patterns disposed on the substrate,
wherein:
each of the plurality of pairs of land patterns includes a first land pattern and a second land pattern,
each of the plurality of pairs of land patterns corresponds to a respective one of the interconnects,
the plurality of pairs of land patterns is disposed such that each of the plurality of interconnects is at least partially interposed between the first land pattern and the second land pattern of the corresponding one of the pairs of land patterns, and
the first land pattern and the second land pattern of each of the plurality of pairs of land patterns have substantially a same thickness as the corresponding one of the interconnects or have a larger thickness than the corresponding one of the interconnects, and
the first land pattern and the second land pattern of each of the plurality of pairs of land patterns are electrically isolated from the corresponding one of the interconnects.

2. The position indicator according to claim 1 , wherein
each of the plurality of interconnects includes a straight line part extending along the substrate, and
the plurality of pairs of land patterns is disposed such that the straight line part of each of the plurality of interconnects is interposed between the first land pattern and the second land pattern of the corresponding one of the pairs of land patterns.

3. The position indicator according to claim 2 , wherein
the straight line part of each of the plurality of interconnects is disposed on a straight line extending along the substrate.

4. The position indicator according to claim 1 , wherein
each of the plurality of interconnects includes a first pad and a second pad that is adjacent the first pad, the first pad and the second pad being configured to be electrically isolated by removal of a solder that electrically couples the first pad and the second pad.

5. The position indicator according to claim 1 , wherein
each of the plurality of interconnects has
a first node and a second node,
a first part and a third part each connected to the first node, and
a second part connected to the second node,

the plurality of pairs of land patterns is disposed such that the first part of each of the plurality of interconnects is at least partially interposed between the first land pattern and the second land pattern of the corresponding one of the pairs of land patterns, and
the second part is interposed between the first and third parts.

6. The position indicator according to claim 5 , wherein
the first part of each of the plurality of interconnects has a straight line part, and
the plurality of pairs of land patterns is disposed such that the straight line part of each of the plurality of interconnects is interposed between the first land pattern and the second land pattern of the corresponding one of the pairs of land patterns.

7. The position indicator according to claim 5 , wherein
the plurality of interconnects includes a first group of the interconnects and a second group of the interconnects,
the first node of each of the interconnects included in the first group is connected to the corresponding one of the capacitors,
the second node of each of the interconnects included in the first group is connected to the coil,
the second node of each of the interconnects included in the second group is connected to the corresponding one of the capacitors,
the first node of each of interconnects included in the second group is connected to the coil, and
respective ones of the interconnects included in the first group and respective ones of the interconnects included in the second group are disposed alternately along the substrate.

8. The position indicator according to claim 1 , wherein
the plurality of interconnects and the plurality of pairs of land patterns are simultaneously formed by etching an electrically-conductive film formed on the substrate.

9. The position indicator according to claim 1 , wherein
the plurality of interconnects and the plurality of pairs of land patterns are formed from the same material.

10. The position indicator according to claim 1 , wherein
a shortest distance between each of the first land pattern and the second land pattern of each of the plurality of pairs land patterns and the corresponding one of the interconnects is a constant value.

11. The position indicator according to claim 1 , wherein
the chassis is pen-shaped,
the substrate is rectangular and has a longer side longer than an inner diameter of the chassis and a shorter side shorter than the inner diameter, and
the substrate is disposed inside of the chassis such that the longer side is in parallel to a longitudinal direction of the chassis.

12. The position indicator according to claim 11 , wherein the plurality of capacitors is disposed on the substrate along the longer side of the substrate.

13. A manufacturing method of a position indicator that includes a chassis and a substrate disposed inside of the chassis, the method comprising:
forming a plurality of interconnects on a surface of the substrate, each of the plurality of interconnects having a first end connected to a first end of a coil and a second end connected to a second end of the coil;
forming a plurality of pairs of land patterns on the surface of the substrate, each of the pairs of land patterns including a first land pattern and a second land pattern and corresponding to one of interconnects, the plurality of pairs of land patterns being disposed such that each of the plurality of interconnects is at least partially interposed between a corresponding one of the pairs of land patterns; and
placing a plurality of capacitors on the plurality of interconnects such that each of the capacitors is placed on a corresponding one of the interconnects to at least partially connect the capacitor to the coil in parallel.

14. The manufacturing method according to claim 13 , wherein:
the forming of the plurality of interconnects and the plurality of pairs of land patterns includes:
depositing an electrically-conductive film on the surface of the substrate, and
etching the electrically-conductive film.

15. The manufacturing method according to claim 14 , further comprising:
cutting one of the interconnects by moving an irradiation point of a laser from the first land pattern to the second land pattern of the corresponding one of the pairs of land patterns.

16. The manufacturing method according to claim 14 , wherein
the forming of the plurality of interconnects forms the plurality of interconnects such that each of the plurality of interconnects has a first pad and a second pad that is adjacent the first pad, the method further comprising:
connecting a first end and a second end of each of the capacitors to the first pad and the second pad, respectively, of one of the plurality of interconnects.

17. The manufacturing method according to claim 14 , wherein
the forming of the plurality of interconnects forms the plurality of interconnects such that each of the plurality of interconnects has a first node and a second node, a first part and a third part each connected to the first node, a

Assignees

• Wacom Co Ltd

Inventors

• Kanzaki Hiromichi
• Ishihara Gunji
• Ito Taketoshi
• Yamaguchi Takashi
• Nagashima Oki

Classifications

• B23K2101/42

  Printed circuits · CPC title

• H05K2203/107

  Using laser light · CPC title

• B23K26/351

  for trimming or tuning of electrical components · CPC title

• H05K1/0292

  having a modifiable lay-out, i.e. adapted for engineering changes or repair (H05K1/0293 takes precedence) · CPC title

• H05K1/181

  associated with surface mounted components · CPC title