Display device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9664966-B2
Application number	US-201514683698-A
Country	US
Kind code	B2
Filing date	Apr 10, 2015
Priority date	Aug 12, 2014
Publication date	May 30, 2017
Grant date	May 30, 2017

Abstract

A method of manufacturing a display device, the method including: forming, on a first surface of a substrate, a gate line and a gate electrode; forming a first dielectric layer on the gate line and the gate electrode; forming a data line, a source electrode and a drain electrode on the first dielectric layer; forming a black matrix layer on the first dielectric layer, the data line, the source electrode, and the drain electrode; radiating ultraviolet light on a second surface of the substrate opposing the first surface, the ultraviolet light developing exposed parts of the black matrix layer to form a black matrix pattern; and etching the first dielectric layer using the black matrix pattern as an etching mask to respectively form a first dielectric pattern on the gate line and a gate dielectric pattern on the gate electrode.

First claim

What is claimed is:

1. A display device comprising:
a gate line structure disposed on a substrate, the gate line structure comprising a gate line and a first dielectric pattern sequentially stacked on the substrate;
a data line structure disposed on the substrate, the data line structure comprising a first dielectric pattern, a first conductive pattern, and a data line sequentially stacked on the substrate;
a thin film transistor disposed on the substrate, the thin film transistor comprising a gate electrode, a gate dielectric pattern, and an active pattern sequentially stacked on the substrate, the thin film transistor further comprising source and drain electrodes disposed on the active pattern; and
a black matrix pattern comprising:
a first region disposed directly on the gate line structure;
a second region disposed directly on the data line structure; and
a third region disposed directly on the thin film transistor,
wherein lateral dimensions of the first region of the black matrix pattern, top of the gate line and the first dielectric pattern of the gate line structure are substantially equal to one another,
wherein lateral dimensions of the second region of the black matrix pattern, the data line and the first dielectric pattern of the data line structure are substantially equal to one another, and
wherein lateral dimensions of the third region of the black matrix pattern and the gate dielectric pattern are substantially equal to one another.

2. The device of claim 1 , wherein:
lateral dimensions of the gate dielectric pattern and the active pattern are substantially equal to one another.

3. The device of claim 1 , wherein:
lateral dimensions of the first conductive pattern of the data line structure and the second region of the black matrix pattern are substantially equal to one another; and
lateral dimensions of the active pattern and the third region of the black matrix pattern are substantially equal to one another.

4. The device of claim 1 , wherein:
a lateral dimension width of the first conductive pattern of the data line structure is greater than a lateral dimension of the second region of the black matrix pattern; and
a lateral dimension of the active pattern is greater than a lateral dimension of the third region of the black matrix pattern.

5. The device of claim 1 , wherein:
the gate line structure further comprises a second dielectric pattern disposed between the first dielectric pattern of the gate line structure and the first region of the black matrix pattern;
the data line structure further comprises a second dielectric pattern disposed between the data line and the second region of the black matrix pattern; and
the thin film transistor further comprises a passivation pattern disposed between the source and drain electrodes and the third region of the black matrix pattern.

6. The device of claim 5 , wherein:
lateral dimensions of the second dielectric pattern and the first region of the black matrix pattern are substantially equal to one another;
lateral dimensions of the second dielectric pattern of the data line structure and the second region of the black matrix pattern are substantially equal to one another; and
lateral dimensions of the passivation pattern and the third region of the black matrix pattern are substantially equal to one another.

7. The device of claim 1 , further comprising:
an organic layer covering the black matrix pattern, the organic layer comprising a hole exposing the drain electrode; and
a pixel electrode electrically connected to the drain electrode exposed via the hole.

8. The device of claim 1 , further comprising:
a color filter covering the black matrix pattern, the color filter comprising a hole exposing the drain electrode; and
a pixel electrode electrically connected to the drain electrode via the hole.

9. The device of claim 1 , wherein each of the gate line, the gate electrode, the data line, the source electrode, and the drain electrode comprises at least one metallic material.

Assignees

• Samsung Display Co Ltd

Inventors

• Shim Seungbo
• Kim Jeong Won
• Park Kwangwoo
• Ju Jinho

Classifications

• H01L27/1288

  Electricity · mapped topic

• G02F2001/136231

  Physics · mapped topic

• G02F2001/136222

  Physics · mapped topic

• H01L29/78669

  Electricity · mapped topic

• G02F1/136209 Primary

  Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element · CPC title