Display panel motherboard, display panel, manufacturing method thereof and display device

US9664936B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9664936-B2
Application numberUS-201514786017-A
CountryUS
Kind codeB2
Filing dateMar 23, 2015
Priority dateOct 30, 2014
Publication dateMay 30, 2017
Grant dateMay 30, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A display panel motherboard, a display panel, a manufacturing method thereof and a display device are provided. The display panel motherboard includes an array substrate provided with a metal lead layer and an protection layer and an opposing substrate provided with a black matrix layer; alignment rulers are respectively disposed in portions of the metal lead layer and the black matrix layer, corresponding to a sealant region; a protrusion is formed in a portion of the protection layer corresponding to the alignment ruler in the metal lead layer, in a thickness direction; and/or the opposing substrate further comprises a spacer layer, and a protrusion is formed in a portion of the spacer layer corresponding to the alignment ruler in the black matrix layer in the thickness direction.

First claim

Opening claim text (preview).

What is claimed is: 1. A display panel motherboard, comprising an array substrate and an opposing substrate, wherein the array substrate comprises a metal lead layer and a protection layer, the opposing substrate comprises a black matrix layer; alignment rulers are respectively disposed in portions of the metal lead layer and the black matrix layer corresponding to a sealant region, wherein a protrusion is formed in a portion of the protection layer corresponding to the alignment ruler in the metal lead layer, in a thickness direction; and/or the opposing substrate further comprises a spacer layer, and a protrusion is formed in a portion of the spacer layer corresponding to the alignment ruler in the black matrix layer in the thickness direction. 2. The display panel motherboard according to claim 1 , wherein a color filter layer is formed on alignment ruler portion of the black matrix layer in the sealant region and forms a part of the spacer layer. 3. The display panel motherboard according to claim 2 , wherein the color filter layer comprises one or more layers selected from a red filter layer, a green filter layer and a blue filter layer. 4. The display panel motherboard according to claim 1 , wherein a planarization layer is also formed above the black matrix layer of the opposing substrate. 5. The display panel motherboard according to claim 1 , wherein the protrusion of the spacer layer includes one protrusion or more than one protrusions, and a recess for accommodating the sealant is formed between more than one protrusions. 6. The display panel motherboard according to claim 1 , wherein the protection layer is directly connected with the sealant. 7. The display panel motherboard according to claim 1 , wherein the spacer layer is directly connected with the sealant. 8. The display panel motherboard according to claim 6 , wherein a recessed portion is formed in the sealant at a position corresponding to the alignment ruler. 9. A display panel, which is obtained by cutting with sealant of the display panel motherboard according to claim 1 . 10. A display device, comprising the display panel according to claim 9 . 11. A method for manufacturing a display panel, comprising: forming a metal lead layer on an array substrate, forming an alignment ruler in a portion of the metal lead layer corresponding to a sealant region, and forming a protection layer on the metal lead layer; and forming a black matrix layer on an opposing substrate, and forming an alignment ruler in a portion of the black matrix layer corresponding to the sealant region, wherein a protrusion is formed in a portion of the protection layer corresponding to the alignment ruler in the metal lead layer, in a cell-assembly direction; and/or a spacer layer is formed above the black matrix layer, and a protrusion is formed in a portion of the spacer layer corresponding to the alignment ruler in the black matrix layer, in the cell-assembly direction. 12. The method for manufacturing the display panel according to claim 11 , wherein a planarization layer is formed on the black matrix layer; and the spacer layer is formed on the planarization layer. 13. The method for manufacturing the display panel according to claim 11 , further comprising: dripping liquid crystal in a display region of the array substrate, coating a sealant at the sealant region of the opposing substrate, and cell-assembling the opposing substrate and the array substrate; and performing alignment calibration and cutting according to the alignment rulers in the metal lead layer and the black matrix layer.

Assignees

Inventors

Classifications

  • Insulating layers (G02F1/1335, G02F1/1337, G02F1/135, G02F1/136 take precedence) · CPC title

  • Filling or closing of cells · CPC title

  • Manufacturing of individual cells out of a plurality of cells, e.g. by dicing · CPC title

  • spacers regularly patterned on the cell subtrate, e.g. walls, pillars (G02F1/133377 takes precedence) · CPC title

  • Physics · mapped topic

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Frequently asked questions

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What does patent US9664936B2 cover?
A display panel motherboard, a display panel, a manufacturing method thereof and a display device are provided. The display panel motherboard includes an array substrate provided with a metal lead layer and an protection layer and an opposing substrate provided with a black matrix layer; alignment rulers are respectively disposed in portions of the metal lead layer and the black matrix layer, c…
Who is the assignee on this patent?
Boe Technology Group Co Ltd, Chengdu Boe Optoelect Tech Co
What technology area does this patent fall under?
Primary CPC classification G02F1/133351. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue May 30 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).