Test method and test apparatus for testing a plurality of blocks in a circuit

Patent metadata

Field	Value
Publication number	US-9664741-B2
Application number	US-201514746973-A
Country	US
Kind code	B2
Filing date	Jun 23, 2015
Priority date	Oct 28, 2014
Publication date	May 30, 2017
Grant date	May 30, 2017

Abstract

Disclosed are a test apparatus and a test method for testing a plurality of blocks in a circuit, the plurality of blocks having identical structures. The test apparatus comprises: a comparing device, configured to collect output responses generated by the plurality of blocks by applying an excitation signal to the plurality of blocks in parallel, compare the output responses of the plurality of blocks to determine whether the output responses of the plurality of blocks are identical, and output results of the comparison of the comparing device; and a determining device, configured to receive the results of the comparison of the comparing device, and determine whether the plurality of blocks have a defect according to the results of the comparison of the comparing device. With the test apparatus and the test method, a process for testing the plurality of blocks having the identical structures may be simplified, and test efficiency may be improved.

First claim

What is claimed is:

1. A test apparatus for testing a plurality of blocks in a circuit, the plurality of blocks having identical structures, the test apparatus comprising:
a comparing device, configured to collect output responses generated by the plurality of blocks by applying an excitation signal to the plurality of blocks in parallel, compare the output responses of the plurality of blocks to determine whether the output responses of the plurality of blocks are identical, and output results of the comparison of the comparing device,
wherein the comparing device compares the output responses of the plurality of blocks sequentially two by two to determine whether the output responses of the plurality of blocks are identical; and
a determining device, configured to receive the results of the comparison of the comparing device, and determine whether the plurality of blocks have a defect according to the results of the comparison of the comparing device,
wherein in response to the output responses of two blocks under comparison being identical, the determining device determines that neither of the two blocks under comparison have the defect,
wherein in response to the output responses of two blocks under comparison being different, the determining device determines that at least one of the two blocks under comparison has the defect, and
wherein in response to the output responses of two blocks under comparison being different, and the output response of one of the two blocks under comparison being identical to an output response of another block in the plurality of blocks other than the two blocks under comparison, the determining device determines that the other one of the two blocks under comparison has the defect.

2. The test apparatus of claim 1 , wherein the plurality of blocks include scan chains having identical structures, each scan chain including at least one scan register, and wherein the excitation signal is applied to the scan chains of the plurality of blocks in parallel.

3. The test apparatus of claim 1 , wherein the comparing device includes an XOR gate provided in the circuit for every two blocks, for comparing the output responses of the two blocks.

4. The test apparatus of claim 3 , further comprising:
a storage device, configured to store the results of the comparison generated by comparing the output responses of the plurality of blocks sequentially two by two, so as to provide the results of the comparison to the determining device.

5. The test apparatus of claim 4 , wherein the storage device includes an OR gate and a D flip-flop register provided in association with each XOR gate, an input of the OR gate being connected to an output of the associated XOR gate, another input of the OR gate being connected to an output of the D flip-flop register, an output of the OR gate being connected to an input of the D flip-flop register, and the output of the D flip-flop register being connected to an input of another D flip-flop register associated with another XOR gate.

6. The test apparatus of claim 1 , wherein the test apparatus is included in the circuit.

7. A test method for testing a plurality of blocks in a circuit, the plurality of blocks having identical structures, the test method comprising:
collecting output responses generated by the plurality of blocks by applying an excitation signal to the plurality of blocks in parallel;
comparing the output responses of the plurality of blocks sequentially two by two, to determine whether the output responses of the plurality of blocks are identical;
in response to the output responses of two blocks under comparison being identical, determining that neither of the two blocks under comparison have a defect;
in response to the output responses of two blocks under comparison being different, determining that at least one of the two blocks under comparison has the defect; and
in response to the output responses of the two blocks under comparison being different, and the output response of one of the two blocks under comparison being identical to an output response of another block in the plurality of blocks other than the two blocks under comparison, determining that the other one of the two blocks under comparison has the defect.

8. The test method of claim 7 , wherein the plurality of blocks include scan chains having identical structures, each scan chain including at least one scan register, and wherein the excitation signal is applied to the scan chains of the plurality of blocks in parallel.

9. The test method of claim 7 , wherein an XOR gate provided for every two blocks is used for comparing the output responses of the two blocks.

10. The test method of claim 9 , further comprising:
storing the results of the comparison generated by comparing the output responses of the plurality of blocks sequentially two by two, for use in determining whether the plurality of blocks have the defect.

11. The test method of claim 10 , wherein the results of the comparison are stored by a storage device including an OR gate and a D flip-flop register provided in association with each XOR gate, an input of the OR gate being connected to an output of the associated XOR gate, another input of the OR gate being connected to an output of the D flip-flop register, an output of the OR gate being connected to an input of the D flip-flop register, and the output of the D flip-flop register being connected to an input of another D flip-flop register associated with another XOR gate.

Assignees

• IBM

Inventors

• Dong Fei
• Gong Shu
• Li hai long
• Lv Yin Peng
• Wang Liu Di

Classifications

• G01R31/3193 Primary

  with comparison between actual response and known fault free response {(receiver details G01R31/31924)} · CPC title

• G01R31/318563 Primary

  Multiple simultaneous testing of subparts · CPC title

• G01R31/31707

  Test strategies (methods for generation of test sequences G01R31/318371) · CPC title

• G01R31/31703 Primary

  Comparison aspects, e.g. signature analysis, comparators (concerning scan tests G01R31/318566; concerning testers G01R31/3193) · CPC title

• G01R31/3172

  Optimisation aspects, e.g. using functional pin as test pin, pin multiplexing · CPC title