Apparatus for processing a serial data stream

Patent metadata

Field	Value
Publication number	US-9660843-B2
Application number	US-201514876206-A
Country	US
Kind code	B2
Filing date	Oct 6, 2015
Priority date	Jun 5, 2015
Publication date	May 23, 2017
Grant date	May 23, 2017

Abstract

A system includes a decision feedback equalizer (DFE). The DFE includes a first summing node, a first synchronization latch, a second synchronization latch, a first feedback latch, and a first feedback shift register. The first summing node is coupled to a data input of the DFE. The first synchronization latch receives data from the first summing node. The second synchronization latch and the first feedback latch receive data from the first synchronization latch. The first feedback shift register is coupled to an output of the second synchronization latch or the first feedback latch. The first feedback shift register includes sequentially coupled shift latches. A first of the shift latches data received from the second synchronization latch or the first feedback latch and provides data to the first summing node. First alternate ones of the shift latches are configured to provide feedback data to the first summing node.

First claim

What is claimed is:

1. A decision feedback equalizer (DFE) circuit, comprising:
an input terminal to receive input data;
a first equalization path and a second equalization path, each comprising:
a summing node coupled to the input terminal to receive input data received at the input terminal;
a first synchronization latch to latch data received from the summing node;
a second synchronization latch to latch data received from the first synchronization latch;
a feedback latch coupled to an output of the first synchronization latch to latch data output from the first synchronization latch, and to output feedback data;
a feedback shift register coupled to an output of one of the second synchronization latch and the feedback latch, to output feedback shift data, the feedback shift register comprising a plurality of sequentially coupled shift latches, wherein:
a first of the shift latches to latch the feedback data and to provide data to the summing node; and
a second of the shift latches to latch data received from the first of the shift latches;

in the first equalization path, the feedback latch, the feedback shift register and the second of the shift latches to provide data to the summing node of the second equalization path; and
in the second equalization path, the feedback latch, the feedback shift register and the second of the shift latches to provide data to the summing node of the first equalization path.

2. The DFE circuit of claim 1 , wherein in each of the first equalization path and the second equalization path, a third of the shift latches is to latch data received from the second of the shift latches and to provide data to the summing node of the equalization path; and
a fourth of the shift latches to latch data received from the third of the shift latches and to provide data to the summing node of the other one of the first and second equalization paths.

3. The DFE circuit of claim 1 , wherein the feedback latch is clocked by a clock that clocks the first synchronization latch shifted by 90 degrees.

4. The DFE circuit of claim 1 , wherein:
in the first equalization path:
the first synchronization latch is clocked by a first clock having a period that is twice a symbol interval time of the input data received at the input terminal;
the second synchronization latch is clocked by a second clock that is an inversion of the first clock; and
the first of the shift latches is clocked by a third clock that is a quadrature phase shifted version of the second clock; and

in the second equalization path:
the first synchronization latch is clocked by the second clock;
the second synchronization latch is clocked by the first clock;
the feedback shift register is clocked by a fourth clock that is an inversion of the third clock.

5. The DFE circuit of claim 4 , further comprising a multiplexer coupled to the second synchronization latch of each equalization path, to selectively route, based on the second clock, data received from the second synchronization latch of each equalization path to an output of the DFE circuit.

6. The DFE circuit of claim 4 , further comprising a multiplexer; and
each of the first equalization path and the second equalization path includes a third synchronization latch to latch data received from the second synchronization latch of the equalization path and to provide data to the multiplexer; and the multiplexer to selectively route, based on the first clock, data received from the third synchronization latch of each equalization path to an output of the DFE circuit.

7. The DFE circuit of claim 1 wherein, in each of the first equalization path and the second equalization path, each successive one of the shift latches is clocked by a clock signal that is an inversion of a clock signal applied to an immediately preceding one of the shift latches.

8. A serializer/deserializer (SERDES) circuit, comprising:
a parallel_in terminal to receive parallel data, and a serial_out terminal to output serialized data;
a serial_in terminal to receive serial data, and a parallel_out terminal to output deserialized data;
deserializer circuitry to deserialize serial_in data received at the serial_in terminal, and provide deserialized data to the parallel_out terminal;
the deserializer circuitry including decision feedback equalizer (DFE) circuitry, comprising
a first equalization path and a second equalization path, each comprising:
a summing node to receive serial data from the serial_in terminal;
a first synchronization latch to latch data received from the summing node;
a second synchronization latch to latch data received from the first synchronization latch;
a feedback latch coupled to an output of the first synchronization latch to latch output data output from the first synchronization latch, and to output feedback data;
a feedback shift register coupled to an output of one of the second synchronization latch and the feedback latch, and to output feedback data, the feedback shift register comprising a plurality of sequentially coupled shift latches, wherein:
a first of the shift latches operable to latch the feedback data and to provide data to the summing node; and
a second of the shift latches to latch data received from the first of the shift latches;

in the first equalization path, the feedback latch, the feedback shift register and the second of the shift latches to provide data to the summing node of the second equalization path; and
in the second equalization path, the feedback latch, the feedback shift register and the second of the shift latches to provide data to the summing node of the first equalization path.

9. The SERDES circuit of claim 8 , wherein in each of the first equalization path and the second equalization path,
a third of the shift latches to latch data received from the second of the shift latches and provide data to the summing node of the equalization path; and
a fourth of the shift latches to latch data received from the third of the shift latches and to provide data to the summing node of the other one of the first and second equalization paths.

10. The SERDES circuit of claim 8 , wherein the feedback latch is clocked by a clock that clocks the first synchronization latch shifted by 90 degrees.

11. The SERDES circuit of claim 8 , wherein:
in the first equalization path:
the first synchronization latch is clocked by a first clock having a period that is twice a symbol interval time of the serial-in data received at the serial_in terminal;
the second synchronization latch is clocked by a second clock that is an inversion of the first clock; and
the first of the shift latches is clocked by a third clock that is a quadrature phase shifted version of the second clock; and

in the second equalization path:
the first synchronization latch is clocked by the second clock;
the second synchronization latch is clocked by the first clock;
the feedback shift register is clocked by a fourth clock that is an inversion of the third clock.

12. The SERDES circuit of claim 11 , further comprising a multiplexer coupled to the second synchronization latch of each equalization path, to selectively route, based on the second clock, data received from the second synchronization latch of each equalization path to the parallel_out terminal.

13. The SERDES circuit of claim 11 ,
further comprising a multiplexer;
each of the first equalization path and the second equalization path includes a third synchronization latch to latch data received from the second synchronization latch of the equalization path and to provide data to the multiplexer; and
the multiplexer is operable

Assignees

• Texas Instruments Inc

Inventors

• Mukherjee Tonmoy Shankar

Classifications

• H04L25/03057 Primary

  with a recursive structure (H04L25/03031 takes precedence) · CPC title

• H04L25/03878 Primary

  Line equalisers; line build-out devices · CPC title

• H04L7/0045

  Correction by a latch cascade · CPC title