Bidirectional packet transfer fail-over switch for serial communication

Patent metadata

Field	Value
Publication number	US-9660835-B2
Application number	US-201414540901-A
Country	US
Kind code	B2
Filing date	Nov 13, 2014
Priority date	Nov 29, 2013
Publication date	May 23, 2017
Grant date	May 23, 2017

Abstract

Disclosed is a bidirectional packet transfer fail-over switch for serial communication. The bidirectional packet transfer fail-over switch for serial communication includes a memory configured to divide packet data, which is transmitted or received for bidirectional communication between a plurality of communication devices, in units of certain data, and store the divided data, and a control unit configured to receive a trigger signal, indicating whether the packet data is received, from the memory, determine a priority according to an order where the packet data is received, and transmit the packet data to another communication device.

First claim

What is claimed is:

1. A bidirectional packet transfer fail-over switch for serial communication comprising:
a memory configured to divide packet data, which is transmitted or received for bidirectional communication between a plurality of communication devices in units of certain data, and to store the divided data; and
a control unit configured to:
receive a trigger signal from the memory, indicating whether the packet data is received,
determine a priority according to an order where the packet data is received, and
transmit the packet data to another communication device,
wherein,
the memory comprises:
a first dual FIFO memory configured to store packet data received from a first communication device,
a first FIFO memory configured to store packet data received from a second communication device, and
a second FIFO memory configured to store packet data received from a third communication device, and
the control unit comprises:
a first transmission control unit configured to read data from the first dual FIFO memory and the second FIFO memory to output the data to the second communication device according to priority, and
a second transmission control unit configured to read data from the first dual FIFO memory and the first FIFO memory to output the data to the third communication device according to priority,
wherein the first dual FIFO memory transfers a packet data presence signal as a trigger signal to the first transmission control unit and the second transmission control unit.

2. The bidirectional packet transfer fail-over switch of claim 1 , wherein,
the memory further comprises a second dual FIFO memory configured to store packet data which is to be output to the first communication device, and
the control unit further comprises:
a first reception control unit configured to store packet data, received from the second communication device, in the first FIFO memory and the second dual FIFO memory, and
a second reception control unit configured to store packet data, received from the third communication device, in the second FIFO memory and the second dual FIFO memory.

3. The bidirectional packet transfer fail-over switch of claim 1 , wherein in transmitting a packet, when the first transmission control unit and the second transmission control unit receive a packet presence trigger signal from the first FIFO memory and the second FIFO memory, after a communication packet of the first dual FIFO memory is transmitted, the first transmission control unit and the second transmission control unit transmit a communication packet of each of the first FIFO memory and the second FIFO memory to the second communication device or the third communication device.

4. The bidirectional packet transfer fail-over switch of claim 1 , wherein a packet size and a character size of a single packet, required by the first dual FIFO memory, the second dual FIFO memory, the first FIFO memory, and the second FIFO memory, are variably adjusted.

5. The bidirectional packet transfer fail-over switch of claim 1 , wherein the first transmission control unit and the second transmission control unit comprise a built-in priority determination algorithm which is designed to preferentially transfer a packet which is first received from each of the first FIFO memory and the second FIFO memory in time.

6. The bidirectional packet transfer fail-over switch of claim 1 , further comprising:
a first serial driver configured to convert a communication media signal level into a Transistor-Transistor Logic (TTL) level signal, for packet data received from a plurality of the communication devices; and
a second serial driver configured to convert a TTL level signal into a communication media signal level, for packet data which is to be transmitted to the plurality of communication devices.

7. The bidirectional packet transfer fail-over switch of claim 1 , further comprising a plurality of input/output terminals for a full-duplex communication transmission/reception structure in which TX or RX is separately provided to a plurality of the communication devices.

8. The bidirectional packet transfer fail-over switch of claim 1 , wherein the control unit is implemented with a programmable logic controller IC, and is designed so that real-time transfer of a communication packet and an idle time between packets are automatically varied at a communication baud rate.

Assignees

• Lsis Co Ltd

Inventors

• Ham Sung Sik

Classifications

• H04L47/6275

  based on priority · CPC title

• H04L49/3036

  Shared queuing · CPC title

• H04L49/103

  using a shared central buffer; using a shared memory · CPC title

• H04L12/6418 Primary

  Hybrid transport · CPC title

• G06F13/40

  Bus structure {(for computer networks G06F15/163; for optical bus networks H04B10/25)} · CPC title