Signal processing apparatus, signal processing method, and signal processing system

Patent metadata

Field	Value
Publication number	US-9660733-B2
Application number	US-201514841834-A
Country	US
Kind code	B2
Filing date	Sep 1, 2015
Priority date	Nov 10, 2014
Publication date	May 23, 2017
Grant date	May 23, 2017

Abstract

A signal processing apparatus includes: a filter; and a filter control circuit, wherein the filter control circuit is configured to: detect a power of signals output from the filter; determine one of a plurality of numerical ranges to which the power belongs; update a filter coefficient of the filter according to a determination result; count a number of the signals having the power of a first value or more; set an invalid area which becomes a target not to be determined for each of one or more boundaries between the plurality of numerical ranges when the number of the signals becomes a second value or more; and control a width of the invalid area based on the number of signals.

First claim

What is claimed is:

1. A signal processing apparatus comprising:
a filter; and
a filter control circuit,
wherein the filter control circuit is configured to:
detect a power of signals output from the filter;
determine one of a plurality of numerical ranges to which the power belongs;
update a filter coefficient of the filter according to a determination result;
count a number of the signals having the power of a first value or more;
set an invalid area which becomes a target not to be determined for each of one or more boundaries between the plurality of numerical ranges when the number of the signals becomes a second value or more; and
control a width of the invalid area based on the number of signals.

2. The signal processing apparatus according to claim 1 , wherein the filter control circuit is configured to control the width of the invalid area so as to be proportional to the number of the signals.

3. The signal processing apparatus according to claim 1 , wherein the filter control circuit is configured to control the width of the invalid area so as to become a fixed width when the number of the signals exceeds a third value.

4. The signal processing apparatus according to claim 1 , wherein the filter control circuit is configured to update the filter coefficient with a variation amount according to an update coefficient.

5. The signal processing apparatus according to claim 1 , wherein the filter control circuit is configured to control an update coefficient corresponding to a variation amount for an update according to the width of the invalid area.

6. The signal processing apparatus according to claim 1 , wherein the filter control circuit is configured to not set the invalid area when the number of the signals is less than the second value.

7. A signal processing method comprising:
detecting a power of signals output from a filter;
determining one of a plurality of numerical ranges to which the power belongs;
updating a filter coefficient of the filter according to a determination result;
counting a number of the signals having the power of a first value or more;
setting an invalid area which becomes a target not to be determined for each of one or more boundaries between the plurality of numerical ranges when the number of the signals becomes a second value or more; and
controlling a width of the invalid area based on the number of signals.

8. The signal processing method according to claim 7 , wherein the width of the invalid area is controlled so as to be proportional to the number of the signals.

9. The signal processing method according to claim 7 , wherein the width of the invalid area is controlled so as to become a fixed width when the number of the signals exceeds a third value.

10. The signal processing method according to claim 7 , wherein the filter coefficient is updated with a variation amount according to an update coefficient.

11. The signal processing method according to claim 7 , wherein an update coefficient corresponding to a variation amount for an update is controlled according to the width of the invalid area.

12. The signal processing method according to claim 7 , wherein the invalid area is not set when the number of the signals is less than the second value.

13. A signal processing system comprising:
a filter;
a processor configured to control the filter based on a program,
wherein the processor is configured to:
detect a power of signals output from the filter;
determine one of a plurality of numerical ranges to which the power belongs;
update a filter coefficient of the filter according to a determination result;
count a number of the signals having the power of a first value or more;
set an invalid area which becomes a target not to be determined for each of one or more boundaries between the plurality of numerical ranges when the number of the signals becomes a second value or more; and
control a width of the invalid area based on the number of signals.

14. The signal processing system according to claim 13 , wherein the processor is configured to control the width of the invalid area so as to be proportional to the number of the signals.

15. The signal processing system according to claim 13 , wherein the processor is configured to control the width of the invalid area so as to become a fixed width when the number of the signals exceeds a third value.

16. The signal processing system according to claim 13 , wherein the processor is configured to update the filter coefficient with a variation amount according to an update coefficient.

17. The signal processing system according to claim 13 , wherein the processor is configured to control an update coefficient corresponding to a variation amount for an update according to the width of the invalid area.

18. The signal processing system according to claim 13 , wherein the processor is configured to not set the invalid area when the number of the signals is less than the second value.

Assignees

• Fujitsu Ltd

Inventors

• Sato Masashi
• Hatae Kazuhiko
• Katou Tomoki
• Koizumi Nobukazu
• Oota Masato
• Ohtomo Yasuo
• Yamazaki Manabu
• Sasaki Daisuke

Classifications

• H04B10/612

  for optical signals modulated with a format different from binary or higher-order PSK [X-PSK], e.g. QAM, DPSK, FSK, MSK, ASK · CPC title

• H03H17/0294

  Variable filters; Programmable filters · CPC title

• H04B10/616 Primary

  Details of the electronic signal processing in coherent optical receivers · CPC title

• H03H21/0012

  Digital adaptive filters · CPC title