Expansion control circuit

Patent metadata

Field	Value
Publication number	US-9660642-B2
Application number	US-201514806240-A
Country	US
Kind code	B2
Filing date	Jul 22, 2015
Priority date	Jul 7, 2015
Publication date	May 23, 2017
Grant date	May 23, 2017

Abstract

An expansion control circuit includes a delay circuit coupled to a first expansion module and a switching circuit coupled to a second expansion module. The switching circuit includes a buffer and a switching module. The buffer is coupled to the first expansion module. The first expansion module outputs a first control signal upon being switched on and outputs a second control signal after a working time. The delay circuit outputs a disconnecting signal upon being switched on. The buffer is switched off upon receiving the disconnect signal. The delay circuit further outputs a connecting signal after a delay time after outputting the disconnecting signal. The buffer is switched on upon receiving the connect signal. The buffer further outputs the second control signal to the switching module upon being switched on. The switching module controls the second expansion module to be switched on v receiving the second control signal.

First claim

What is claimed is:

1. An expansion control circuit comprising:
a delay circuit, having a delay time, configured to couple to a first expansion module; and
a switching circuit having:
a buffer configured to couple to the first expansion module, and
a switching module configured to couple to a second expansion module;

wherein the first expansion module is configured to:
output a first control signal upon being switched on, and
output a second control signal after a preset working time;

wherein the delay circuit is configured to:
enable the buffer to be switched off subsequent to being switched on, and
enable the buffer to be switched on subsequent to being switched off;

wherein the buffer is configured to output the second control signal to the switching module upon being switched on; and
wherein the switching module is configured to control the second expansion module to be switched on upon receiving the second control signal.

2. The expansion control circuit of claim 1 , wherein the switching module comprises a first field effect transistor (FET) and a second FET, the first FET is switched off after receiving the second control signal, and the second FET is switched on after the first FET is switched off.

3. The expansion control circuit of claim 2 , wherein the second FET is configured to output a third control after being switched on and the second expansion module is configured to be switched on after receiving the third control signal.

4. The expansion control circuit of claim 3 , wherein the third control signal is a low level signal.

5. The expansion control circuit of claim 2 , wherein the first FET is an n-channel metal-oxide semiconductor (MOS).

6. The expansion control circuit of claim 5 , wherein the second FET is an n-channel MOS, a drain terminal of the first FET is coupled to a gate terminal of the second FET, and a drain terminal of the second FET is configured to the second expansion module.

7. The expansion control circuit of claim 6 , wherein the buffer comprises a receiving terminal and a sending terminal, the receiving terminal is configured to couple to the first expansion module, and the sending terminal is configured to couple to a gate terminal of the first FET.

8. The expansion control circuit of claim 1 , wherein the preset working time is equal to or less than the delay time.

9. The expansion control circuit of claim 1 , wherein the delay circuit comprises a delay chip coupled to the buffer, the delay chip is configured to couple to the first expansion module, the delay chip is configured to output a disconnecting signal after being switched on and is configured to output a connecting signal after the delay time, and the buffer is configured to be switched off after receiving the disconnecting signal and be switched on receiving the connecting signal.

10. The expansion control circuit of claim 9 , wherein the delay circuit further comprises a switching member, the switching member is coupled to the delay chip, and the delay chip is configured to be switched on after the switching member is switched on.

11. An expansion control circuit comprising:
a delay circuit configured to couple to a first expansion module; and
a switching circuit having:
a buffer configured to couple to the first expansion module, and
a switching module configured to couple to a second expansion module;

wherein the first expansion module is configured to:
output a first control signal upon being switched on, and
output a second control signal after a preset working time;

wherein the delay circuit is configured to:
output a disconnecting signal upon being switched on, and
output a connecting signal after a delay time after outputting the disconnecting signal;

wherein the buffer is configured to:
be switched off upon receiving the disconnecting signal,
be switched on upon receiving the connecting signal, and
output the second control signal to switching module upon being switched on; and

wherein the switching module is configured to control the second expansion module to be switched on upon receiving the second control signal.

12. The expansion control circuit of claim 11 , wherein the switching module comprises a first field effect transistor (FET) and a second FET, the first FET is switched off after receiving the second control signal, and the second FET is switched on after the first FET is switched off.

13. The expansion control circuit of claim 12 , wherein the first FET is an n-channel metal-oxide semiconductor (MOS).

14. The expansion control circuit of claim 13 , wherein the second FET is an n-channel MOS, a drain terminal of the first FET is coupled to a gate terminal of the second FET, and a drain terminal of the second FET is configured to the second expansion module.

15. The expansion control circuit of claim 13 , wherein the buffer comprises a receiving terminal and a sending terminal, the receiving terminal is configured to couple to the first expansion module, and the sending terminal is configured to couple to a gate terminal of the first FET.

16. The expansion control circuit of claim 11 , wherein the preset working time is equal to the delay time.

17. The expansion control circuit of claim 11 , wherein the delay circuit comprises a delay chip coupled to the buffer, the delay chip is configured to couple to the first expansion module, and the delay chip is configured to output the disconnecting signal after being switched on and is configured to output the connecting signal after the delay time.

18. The expansion control circuit of claim 17 , wherein the delay circuit further comprises a switching member, the switching member is coupled to the delay chip, and the delay chip is configured to be switched on after the switching member is switched on.

19. The expansion control circuit of claim 11 , wherein the first control signal is a low level signal.

20. The expansion control circuit of claim 11 , wherein the second control signal is a high level signal.

Assignees

• Hong Fu Jin Prec Ind (Shenzhen) Co Ltd
• Hon Hai Prec Ind Co Ltd

Inventors

• Chen Po-Jung
• Yang Meng-Liang

Classifications

• H03K17/133

  in field-effect transistor switches · CPC title

• H03K17/04163

  in field-effect transistor switches · CPC title

• H03K2005/00013

  Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse · CPC title

• H03K17/04106

  in field-effect transistor switches (H03K17/0412, H03K17/0416 take precedence) · CPC title

• H03K17/223

  in field-effect transistor switches · CPC title