Resistor controlled timer circuit with gain ranging

Patent metadata

Field	Value
Publication number	US-9660628-B2
Application number	US-201414563559-A
Country	US
Kind code	B2
Filing date	Dec 8, 2014
Priority date	Dec 8, 2014
Publication date	May 23, 2017
Grant date	May 23, 2017

Abstract

A timer circuit is provided comprising: a resistor; a programmable gain circuit coupled to amplify the reference level based upon a resistor and a selected gain; a detection circuit coupled to identify the amplified reference level based upon a resistor; a selection circuit configured to select the gain based at least in part upon the identified amplified reference level based upon a resistor; a comparator circuit configured to transition between providing a signal having a first value and providing a signal having a second value based at least in part upon comparisons of a reactive circuit element excitation level with the amplified reference level based upon a resistor and with a second reference level; and reactive circuit element excitation circuit configured to reverse excitation of the reactive circuit element in response to the comparator circuit transitioning between providing the signal having the first value and providing the signal having the second value.

First claim

The invention claimed is:

1. A circuit comprising:
a resistor a first variable current source coupled to provide a selectable range of current levels to the resistor to produce a resistor voltage level;
a voltage level detection circuit coupled to identify a resistor voltage level;
a selection circuit configured to select a current level based at least in part upon the identified resistor voltage level;
a second reference voltage;
a capacitor;
a comparator circuit configured to transition between providing a signal having a first value and providing a signal having a second value based at least in part upon comparisons of a capacitor voltage level with the identified resistor voltage level and with the second reference voltage; and
a capacitor excitation circuit configured to reverse excitation of the capacitor in response to the comparator circuit transitioning between providing the signal having the first value and providing the signal having the second value.

2. The circuit of claim 1 further including:
a switch to select from among multiple current sources to provide a current value to the resistor to produce the resistor voltage level.

3. The circuit of claim 1 further including;
a counter circuit; and
an interface circuit that is configured to provide an indication of each occurrence of the comparator circuit providing the signal having the first value and to provide an indication of each occurrence of the comparator circuit providing the signal having the second value;
wherein the counter circuit advances a count to a prescribed number of indications; and
wherein the selection circuit is configured to determine whether the resistor voltage level is within a prescribed voltage range and to scale a current level of the first current source by a first scaling factor and to scale a divider ratio of the counter circuit by second scaling factor that is approximately an inverse of the first scaling factor; in response to the determination that the resistor voltage level is outside of a prescribed voltage range.

4. The circuit of claim 1 further including;
multiple candidate first current sources including a base current source;
switch circuitry to selectively individually couple each current source to act as the first current source;
wherein the selection circuitry configured to search for a candidate first current source that results in a resistor voltage level within a prescribed voltage range by causing the switch circuitry to select successive candidate first current sources and by causing the detector to sample successive resistor voltage levels for the successive candidate first current sources, at least until a candidate first current source is identified that results in a resistor voltage level sample falling within the prescribed voltage range;
wherein the selection circuitry is configured to adjust a divider ratio of the counter circuit by a scaling factor that is approximately in inverse proportion to a ratio between a current value of the identified candidate first current source and a value of a base first current source.

5. The circuit of claim 1 , further including:
a second current source; and
a current sink; wherein the capacitor excitation circuit includes a first switch configured to alternately couple the capacitor to the second current source to charge the capacitor voltage and couple the capacitor to the current sink to discharge the capacitor voltage.

6. The circuit of claim 1 further including:
a second current source; and
a current sink;
wherein the capacitor excitation circuit includes a first switch that includes an inverter circuit that includes a voltage pull-up device and a voltage pull-down device, wherein the voltage pull-up device is configured to couple the capacitor to the second current source to charge the capacitor voltage, and wherein the voltage pull-down device is configured to couple the capacitor to the current sink to discharge the capacitor voltage.

7. The circuit of claim 1 , further including:
wherein the comparator circuitry includes a first comparator coupled to compare the capacitor voltage to the resistor voltage; and
wherein the comparator circuitry includes a second comparator coupled to compare the capacitor voltage to the second reference voltage.

8. The circuit of claim 1 further including:
a counter circuit; and
an interface circuit that includes a latch circuit that is configured to provide indications of occurrences of each of the first and second values; wherein the counter counts up to a prescribed number of indications.

9. The circuit of claim 1 , a counter circuit;
wherein the selection circuit is further configured to change a divider ratio of the counter circuit in substantially an inverse proportion to the selected current level.

10. The of claim 1 ,
wherein the detection circuit includes an analog to digital converter (ADC).

11. A circuit modulation method comprising:
providing a first current source;
conducting a current provided by the first current source through a resistor to produce a resistor voltage;
determining the resistor voltage level;
selecting an adjustment of the resistor voltage level at least in part upon the determined resistor voltage level;
adjusting the resistor voltage level based upon the selected adjustment;
coupling a comparator circuit to compare a capacitor voltage to the adjusted resistor voltage and to compare the capacitor voltage to a second voltage;
changing a ramp direction of the capacitor voltage based upon the comparison of the capacitor voltage with the adjusted resistor voltage and the second voltage.

12. The method of claim 11 further including:
storing an indication of the ramp direction of the capacitor voltage, when the capacitor voltage is between the resistor voltage and the second reference voltage.

13. The method of claim 11 , wherein adjusting the resistor voltage level includes changing current through the resistor.

14. The method of claim 11 further including:
advancing a counter to a prescribed number of occurrences of discharging the capacitor and charging the capacitor.

15. The method of claim 11 , wherein the acts of determining and selecting are performed in a startup mode before charging and discharging of the capacitor.

Assignees

• Analog Devices Global

Inventors

• Almazan Sherwin Paul Roldan
• Spalding Jr George Redfield

Classifications

• H03K5/153

  Arrangements in which a pulse is delivered at the instant when a predetermined characteristic of an input signal is present or at a fixed time interval after this instant (switching at zero crossing H03K17/13) · CPC title

• H03K5/1534 Primary

  Transition or edge detectors · CPC title

• H03K3/0231 Primary

  Astable circuits {(H03K3/0315 takes precedence)} · CPC title

• H03K17/6871

  the output circuit comprising more than one controlled field-effect transistor · CPC title