Semiconductor apparatus

Patent metadata

Field	Value
Publication number	US-9660617-B2
Application number	US-201514665957-A
Country	US
Kind code	B2
Filing date	Mar 23, 2015
Priority date	Dec 5, 2014
Publication date	May 23, 2017
Grant date	May 23, 2017

Abstract

A semiconductor apparatus includes a pipe input/output signal generation block configured to generate a plurality of pipe input signals and a plurality of pipe output signals according to a pipe enable signal, and be initialized according to an error detection signal; a pipe latch group including a plurality of pipe latches, each of the plurality of pipe latches being configured to receive and store an input signal according to a corresponding pipe input signal and output a stored signal as an output signal according to a corresponding pipe output signal; and an error detection block configured to generate the error detection signal according to a pipe end signal, the pipe enable signal, the plurality of pipe input signals and the plurality of pipe output signals.

First claim

What is claimed is:

1. A semiconductor apparatus comprising:
a pipe input/output signal generation block configured to generate a plurality of pipe input signals and a plurality of pipe output signals according to a pipe enable signal, and be initialized according to an error detection signal;
a pipe latch group including a plurality of pipe latches, each of the plurality of pipe latches being configured to receive and store an input signal according to a corresponding pipe input signal and output a stored signal as an output signal according to a corresponding pipe output signal; and
an error detection block configured to generate the error detection signal according to a pipe end signal, the pipe enable signal, the plurality of pipe input signals and the plurality of pipe output signals,
wherein the error detection block compares a number of pipe input signals enabled among the plurality of pipe input signals and a number of pipe output signals enabled among the plurality of pipe output signals after the pipe enable signal is enabled to until the pipe end signal is enabled, and generates the error detection signal.

2. The semiconductor apparatus according to claim 1 , wherein each of the plurality of pipe latches are initialized according to the error detection signal.

3. The semiconductor apparatus according to claim 1 , wherein the pipe input/output signal generation block comprises:
a pipe input signal generation unit configured to sequentially enable the plurality of pipe input signals in response to the pipe enable signal; and
a pipe output signal generation unit configured to enable a corresponding pipe output signal among the plurality of pipe output signals, after a preset time has passed, when one of the plurality of pipe input signals is enabled in response to the pipe enable signal.

4. The semiconductor apparatus according to claim 1 , wherein the error detection block comprises:
an enable signal generation unit configured to generate a detection enable signal enabled when the pipe enable signal is enabled and is disabled when the pipe end signal is enabled;
a first counting unit configured to generate first counting codes corresponding to the number of pipe input signals enabled among the plurality of pipe input signals during an enable period of the detection enable signal;
a second counting unit configured to generate second counting codes corresponding to the number of pipe output signals enabled among the plurality of pipe output signals during the enable period of the detection enable signal; and
an error detection signal generation unit configured to compare the first and second counting codes, and generate the error detection signal.

5. The semiconductor apparatus according to claim 4 , wherein the error detection signal generation unit outputs a result of a comparison of the first and second counting codes as the error detection signal when the detection enable signal is disabled.

6. A semiconductor apparatus comprising:
a pipe input/output signal generation block configured to sequentially enable a plurality of pipe input signals and a plurality of pipe output signals according to a read signal, and be initialized according to an error detection signal;
a pipe latch group configured to receive and store data according to a pipe input signal enabled among the plurality of pipe input signals, and output stored data as an output signal according to a pipe output signal enabled among the plurality of pipe output signals; and
an error detection block configured to generate the error detection signal according to a precharge signal, the read signal, the plurality of pipe input signals and the plurality of pipe output signals,
wherein the error detection block compares a number of pipe input signals enabled among the plurality of pipe input signals and a number of pipe output signals enabled among the plurality of pipe output signals after the read signal is enabled to until the precharge signal is enabled, and generates the error detection signal.

7. The semiconductor apparatus according to claim 6 , wherein the error detection block comprises:
an enable signal generation unit configured to generate a detection enable signal enabled when the read signal is enabled and retains an enabled state until the discharge signal is enabled;
a first counting unit configured to count the number of pipe input signals enabled among the plurality of pipe input signals during an enable period of the detection enable signal, and generate first counting codes;
a second counting unit configured to count the number of pipe output signals enabled among the plurality of pipe output signals during the enable period of the detection enable signal, generate second counting codes; and
an error detection signal generation unit configured to disable the error detection signal when the first counting codes and the second counting codes are the same when the detection enable signal is disabled, and enable the error detection signal when the first counting codes and the second counting codes are different and the detection enable signal is disabled.

8. The semiconductor apparatus according to claim 7 , wherein the error detection signal generation unit comprises:
a comparing section configured to output a comparison result of the first counting codes and the second counting codes as a determination signal; and
an output section configured to output the determination signal as the error detection signal when the detection enable signal is disabled.

9. A semiconductor apparatus comprising:
a pipe input/output signal generation block configured to generate first to fourth pipe input signals and first to fourth pipe output signals according to a pipe enable signal and be initialized according to an error detection signal;
a pipe latch group configured to receive and store an input signal according to the first to fourth input signals and output the stored signal as an output signal according to the first to fourth pipe output signals; and
an error detection block configured to generate the error detection signal according to the pipe enable signal, a pipe end signal, the first to fourth pipe input signals and the first to fourth pipe output signals,
wherein the error detection block compares a number of pipe input signals enabled among the first to fourth pipe input signals to a number of pipe output signals enabled among the first to fourth pipe output signals when the pipe enable signal is enabled.

10. The semiconductor apparatus according to claim 9 , further comprising:
a first counting unit configured to count pipe input signals among the first to fourth pipe input signals to generate first counting codes.

11. The semiconductor apparatus according to claim 10 , further comprising:
a second counting unit configured to count pipe output signals enabled among the first to fourth pipe output signals to generate second counting codes.

12. The semiconductor apparatus according to claim 11 , further comprising:
an error detection signal generation unit configured to compare the first counting codes to the second counting codes and output a comparison result as the error detection signal.

13. The semiconductor apparatus according to claim 12 , wherein the error detection signal generation unit comprises:
a comparing section configured to enable a determination signal when the first counting codes are different from the second counting codes.

14. The semiconductor apparatus according to claim 12 , wherein the wherein the error detection signal generation unit comprises:
an output section configured to receive a determinatio

Assignees

• Sk Hynix Inc

Inventors

• Kong Kyu Bong
• Lee Geun Il

Classifications

• G11C7/1087

  Data input latches · CPC title

• G11C7/1093

  Input synchronization · CPC title

• H03K21/026

  comprising logic circuits · CPC title

• G11C7/1039

  using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers · CPC title

• H03K3/0375 Primary

  provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails (digital storage cells each combining volatile and non-volatile storage properties G11C14/00) · CPC title