Amplifier with compensation of gain in low frequencies

Patent metadata

Field	Value
Publication number	US-9660601-B2
Application number	US-201615136644-A
Country	US
Kind code	B2
Filing date	Apr 22, 2016
Priority date	May 8, 2015
Publication date	May 23, 2017
Grant date	May 23, 2017

Abstract

An amplifier includes a differential amplifier and a compensator. A differential amplifier includes a current source and paired transistors. The paired transistors generate an output signal by dividing a source current supplied by the current source into emitter currents of the paired transistors in response to a difference between an input signal and a reference signal. A compensator includes an amplifying transistor and a feedback circuit that feeds a collector current output from a collector of the amplifying transistor back to a base of the amplifying transistor therethrough. The compensator generates the reference signal at a base of the amplifying transistor. The compensator decreases power consumption of the amplifying transistor when the collector current increases, and increases the power consumption of the amplifying transistor when the collector current decreases. The compensator suppresses a peaking of gain in a low frequency band.

First claim

What is claimed is:

1. An amplifier that amplifies an input signal and outputs a differential signal derived from the input signal, comprising:
a differential amplifier including a first current source, a first paired transistor, and a second paired transistor, the first current source supplying a first source current to the first paired transistor and the second paired transistor, the first paired transistor receiving the input signal at a base thereof, the second paired transistor receiving a reference signal at a base thereof, the first paired transistor and the second paired transistor being configured to divide the first source current into a first current that flows through an emitter of the first paired transistor and a second current that flows through an emitter of the second transistor in response to a difference between the input signal and the reference signal, the differential amplifier being configured to output a voltage difference between collectors of the first paired transistor and the second paired transistor as the differential signal, and
a compensator including an amplifying transistor and a feedback circuit that feeds an output signal generated at a collector of the amplifying transistor back to a base of the amplifying transistor therethrough, the compensator being configured to output the reference signal generated at the base of the amplifying transistor,
wherein the compensator decreases a power consumption of the amplifying transistor when a collector current output from the collector of the amplifying transistor increases, and increases the power consumption of the amplifying transistor when the collector current output from the collector of the amplifying transistor decreases.

2. The amplifier according to claim 1 , wherein the compensator further includes:
a second current source connected with the collector of the amplifying transistor, and
a bias circuit connected with an emitter of the amplifying transistor, the bias circuit being configured to generate a bias voltage by making an emitter current output from the emitter of the amplifying transistor flow thereinto,
wherein the compensator provides a sum of the bias voltage and a voltage between the base of the amplifying transistor and the emitter of the amplifying transistor as the reference signal.

3. The amplifier according to claim 2 , wherein
the bias circuit includes a diode having an anode and a cathode, and
wherein the anode of the diode is connected with the emitter of the amplifying transistor, and the cathode of the diode is grounded.

4. The amplifier according to claim 3 , wherein the first paired transistor, the second paired transistor, the amplifying transistor, and the diode are provided on a single semiconductor die.

5. The amplifier according to claim 1 , wherein
the first paired transistor, the second paired transistor, and the amplifying transistor are provided on a single semiconductor die.

6. The amplifier according to claim 1 , wherein
the first paired transistor, the second paired transistor, and the amplifying transistor are hetero junction bipolar transistors.

7. An amplifier that amplifies an input signal and outputs a differential signal derived from the input signal, comprising:
a differential amplifier including a first current source, a first paired transistor, and a second paired transistor, the first current source supplying a first source current to the first paired transistor and the second paired transistor, the first paired transistor receiving the input signal at a base thereof, the second paired transistor receiving a reference signal at a base thereof, the first paired transistor and the second paired transistor being configured to divide the first source current into a first current that flows through an emitter of the first paired transistor and a second current that flows through an emitter of the second paired transistor in response to a difference between the input signal and the reference signal, the differential amplifier being configured to output a voltage difference between collectors of the first transistor and the second transistor as the differential signal, and
a compensator including an amplifying transistor, an emitter follower, and a feedback circuit, the amplifying transistor having a collector connected with an input terminal of the emitter follower, the feedback circuit being configured to feed an output signal output from the emitter follower back to a base of the amplifying transistor therethrough, the compensator being configured to output the reference signal generated at the base of the second transistor,
wherein the compensator decreases a power consumption of the amplifying transistor when a collector current of the amplifying transistor increases, and increases the power consumption of the amplifying transistor when the collector current of the amplifying transistor decreases.

8. The amplifier according to claim 7 , wherein the compensator further includes:
a second current source connected with the collector of the amplifying transistor, and
a bias circuit connected with an emitter of the amplifying transistor, the bias circuit being configured to generate a bias voltage by making an emitter current output from the emitter of the amplifying transistor flow thereinto,
wherein the compensator provides a sum of the bias voltage and a voltage between the base of the amplifying transistor and the emitter of the amplifying transistor as the reference signal.

9. The amplifier according to claim 8 , wherein
the bias circuit includes a diode having an anode and a cathode, and
wherein the anode of the diode is connected with the emitter of the second transistor, and the cathode of the diode is grounded.

10. The amplifier according to claim 9 , wherein
the first paired transistor, the second paired transistor, the amplifying transistor, and the diode are provided on a single semiconductor die.

11. The amplifier according to claim 7 , wherein
the first paired transistor, the second paired transistor, and the amplifying transistor are provided on a single semiconductor die.

12. The amplifier according to claim 7 , wherein
the first paired transistor, the second paired transistor, and the amplifying transistor are hetero-junction bipolar transistors.

13. An amplifier that amplifies a differential input signal and outputs a differential output signal derived from the differential input signal, the differential input signal consisting of a positive-phase input signal and a negative-phase input signal, the differential output signal consisting of a positive-phase output signal and a negative-phase output signal, comprising:
a first differential amplifier including a first current source, a first paired transistor, and a second paired transistor, the first current source supplying a first source current to the first paired transistor and the second paired transistor, the first paired transistor receiving the positive-phase input signal at a base thereof, the second paired transistor receiving a first reference signal at a base thereof, the first paired transistor and the second paired transistor being configured to divide the first source current into a first current that flows through an emitter of the first paired transistor and a second current that flows through an emitter of the second transistor in response to a difference between the positive-phase input signal and the reference signal, the first differential amplifier being configured to output a voltage at a collector of the first paired transistor as the negative-phase output signal,
a second differential amplifier including a second current

Assignees

• Sumitomo Electric Industries

Inventors

• Tanaka Keiji
• Sugimoto Yoshiyuki

Classifications

• H03F2200/24

  the supply or bias voltage or current at the source side of a FET being continuously controlled by a controlling signal · CPC title

• H03F2203/45026

  One or more current sources are added to the amplifying transistors in the differential amplifier · CPC title

• H03F3/213

  in integrated circuits · CPC title

• H03F2203/45288

  Differential amplifier with circuit arrangements to enhance the transconductance · CPC title

• H03F2200/153

  Feedback used to stabilise the amplifier · CPC title