High reliability etched-facet photonic devices

Patent metadata

Field	Value
Publication number	US-9660419-B2
Application number	US-201414296139-A
Country	US
Kind code	B2
Filing date	Jun 4, 2014
Priority date	Feb 18, 2005
Publication date	May 23, 2017
Grant date	May 23, 2017

Abstract

Semiconductor photonic device surfaces are covered with a dielectric or a metal protective layer. The protective layer covers the entire device, including regions near facets at active regions, to prevent bare or unprotected semiconductor regions, thereby to form a very high reliability etched facet photonic device.

First claim

What is claimed is:

1. A process for fabricating a photonic device, comprising:
forming on a top surface of a substrate a semiconductor structure comprising an active layer;
dry etching at least one facet in said semiconductor structure defining at least one side surface of said semiconductor structure and at least one side wall in said semiconductor structure defining remaining side surfaces of said semiconductor structure, wherein said etching exposes said active layer;
directly covering all side and top surfaces of said semiconductor structure with a single continuous protective layer of a dielectric material including directly covering said active layer at said at least one etched facet;
opening a contact window in said single continuous protective layer at said top surface of said semiconductor structure; and
depositing a metal layer to cover said contact window and overlap onto said single continuous protective layer to provide an electrically conductive contact on a top surface of said semiconductor structure;
wherein all side and top surfaces of said semiconductor structure remain directly covered with said single continuous protective layer and said metal layer after completion of said process to seal said semiconductor structure.

2. The process of claim 1 , wherein said substrate is formed of one of: InP; GaAs; and GaN.

3. The process of claim 1 , wherein forming on a top surface of a substrate a semiconductor structure comprises:
depositing a first cladding layer on said top surface of said substrate;
depositing said active layer on said first cladding layer; and
depositing a second cladding layer on said active layer.

4. The process of claim 3 , wherein said first cladding layer and said second cladding layer are formed of InP.

5. The process of claim 3 , wherein said active layer is formed of AlInGaAs.

6. The process of claim 3 , wherein forming on a top surface of a substrate a semiconductor structure further comprises:
depositing a cap layer on a top surface of said second cladding layer.

7. The process of claim 6 , wherein said cap layer is formed of InGaAs.

8. The process of claim 6 , further comprising:
depositing a first dielectric layer on a top surface of said cap layer.

9. The process of claim 8 , wherein said first dielectric layer is formed of SiO 2 .

10. The process of claim 8 , wherein dry etching said semiconductor structure comprises:
etching said semiconductor structure to form said at least one etched facet and said at least one side wall; and
etching said semiconductor structure to form a ridge having a top surface and a plurality of side surfaces, wherein said top surface of said ridge comprises a top surface of said cap layer.

11. The process of claim 10 , further comprising:
depositing a second dielectric layer on said top and side surfaces of said ridge and said at least one side wall and said at least one etched facet.

12. The process of claim 11 , wherein said second dielectric layer is formed of SiO 2 .

13. The process of claim 11 , wherein said second dielectric layer is also deposited on exposed portions of said substrate extending outward from said at least one wall and said at least one etched facet.

14. The process of claim 11 , wherein opening a contact window in said single continuous protective layer comprises:
etching said single continuous protective layer on at least a portion of said top surface of said ridge to expose at least a portion of said cap layer and create said contact window.

15. The process of claim 14 , wherein depositing a metal layer to cover said contact window comprises:
depositing said metal layer in said contact window to form said electrically conductive contact for said photonic device.

16. The process of claim 15 , wherein said metal layer is at least partially formed of Au.

17. The process of claim 15 , wherein said metal layer extends beyond said contact window onto said single continuous protective layer to seal said contact window.

18. The process of claim 1 , further comprising:
depositing a second metal layer on a bottom surface of said substrate opposite said semiconductor structure to form second electrically conductive contact for said photonic device.

19. The process of claim 1 , further comprising:
singulating said photonic device along singulation edges formed in said substrate.

20. The process of claim 19 , wherein said single continuous protective layer covers exposed portions of said substrate extending to said singulation edges.

Assignees

• Macom Tech Solutions Holdings Inc

Inventors

• Behfar Alex A

Classifications

• H01S5/22

  having a ridge or stripe structure · CPC title

• H01S5/0282

  Passivation layers or treatments · CPC title

• H01S5/0202

  Cleaving · CPC title

• H01S5/0201

  Separation of the wafer into individual elements, e.g. by dicing, cleaving, etching or directly during growth · CPC title

• G02F1/17

  based on variable-absorption elements not provided for in groups G02F1/015 - G02F1/169 · CPC title