Integration of spintronic devices with memory device

Patent metadata

Field	Value
Publication number	US-9660183-B2
Application number	US-201615052796-A
Country	US
Kind code	B2
Filing date	Feb 24, 2016
Priority date	Feb 26, 2015
Publication date	May 23, 2017
Grant date	May 23, 2017

Abstract

A device and a method of forming a device are presented. A substrate is provided. The substrate includes circuit component formed on a substrate surface. Back end of line processing is performed to form an upper inter level dielectric (ILD) layer. The upper ILD layer includes a plurality of ILD levels. A plurality of magnetic tunneling junction (MTJ) stacks is formed in between adjacent ILD levels of the upper ILD layer. The plurality of MTJ stacks include a first MTJ stack having a first free layer, a first tunneling barrier layer and a first fixed layer. The first free layer is perpendicular to the first tunneling layer and fixed layer in the plane of the substrate surface. The plurality of MTJ stacks also include a second MTJ stack having a second free layer, a second tunneling barrier layer and a second fixed layer.

First claim

What is claimed is:

1. A method of forming a device comprising:
providing a substrate comprising circuit component formed on a substrate surface;
performing back end of line processing to form an upper inter level dielectric (ILD) layer over the substrate, wherein the upper ILD layer comprises a plurality of ILD levels; and
forming a plurality of magnetic tunneling junction (MTJ) stacks in between adjacent ILD levels of the upper ILD layer, wherein the plurality of the MTJ stacks comprise
a first MTJ stack having a first free layer, a first tunneling barrier layer and a first fixed layer, wherein the first free layer is perpendicular to the first tunneling layer and fixed layer in the plane of the substrate surface, and
a second MTJ stack having a second free layer, a second tunneling barrier layer and a second fixed layer, wherein the first free layer is perpendicular to the second free layer in the plane of the substrate surface.

2. The method of claim 1 , wherein:
the first free layer comprises a first long axis and a first short axis;
the second free layer comprises a second long axis and a second short axis; and
the first long axis is aligned with the second short axis and the first short axis is aligned with the second long axis.

3. The method of claim 1 wherein the plurality of the MTJ stacks further comprise:
a third MTJ stack having a third free layer, a third tunneling barrier layer and a third fixed layer.

4. The method of claim 3 wherein:
the second free layer comprises a second long axis and a second short axis;
the third free layer comprises a third long axis and a third short axis; and
a first aspect ratio is defined by AR 1 which is equal to second long axis/second short axis and a second aspect ratio is defined by AR 2 which is equal to third long axis/a third short axis.

5. The method of claim 4 wherein the second long axis is different from the third long axis and the second short axis of the second free layer is different from the third short axis.

6. The method of claim 5 wherein AR 1 is about 2 to 3 and AR 2 is about 1 to 3.

7. The method of claim 1 wherein forming the plurality of MTJ stacks in between adjacent ILD levels comprises:
forming a plurality of openings in a lower dielectric layer of a lower ILD level of the adjacent ILD levels;
forming a bottom electrode layer over the lower dielectric layer and fills the openings;
planarizing the bottom electrode layer to form bottom electrodes in the openings and removing excess bottom electrode layer in areas other than the openings;
depositing remaining MTJ stack layers over the lower dielectric layer and the bottom electrodes; and
patterning the remaining MTJ stack layers to form a plurality of MTJ stacks and a top electrode of the MTJ stacks over the bottom electrodes.

8. The method of claim 7 where depositing the remaining MTJ stack layers comprises sequentially depositing a fixed layer, a tunneling barrier layer, a free layer and a top electrode layer over the lower dielectric layer and the bottom electrodes.

9. The method of claim 8 wherein patterning the remaining MTJ stack layers comprises:
patterning a first portion of the top electrode layer and free layer using a first mask having a first opening, wherein patterning the first portion forms the first free layer and a first top electrode; and
patterning the patterned first portion and a second portion of the top electrode layer and free layer using a second mask having a second opening, wherein patterning of the patterned first portion forms the first MTJ stack having the first top electrode, and patterning of the second portion forms the second MTJ stack having a second top electrode.

10. The method of claim 9 wherein the second opening is larger than the first opening.

11. The method of claim 10 further comprising patterning a third portion of the top electrode layer and free layer using the second mask having a third opening during the patterning of the patterned first portion and the second portion, wherein patterning of the third portion forms a third MTJ stack having a third free layer, a third tunneling barrier layer, a third fixed layer a third top electrode.

12. The method of claim 11 wherein the second free layer has a second aspect ratio and the third free layer has a third aspect ratio, wherein the first aspect ratio is different from the third aspect ratio.

13. The method of claim 11 comprising:
forming an intermediate dielectric layer over the lower dielectric layer and covers the patterned MTJ stacks; and
performing a planarizing process to form planar top surface between top of the MTJ stacks and the intermediate dielectric layer.

14. The method of claim 13 further comprising forming first, second and third metal lines over the intermediate dielectric layer, wherein the first, second and third metal lines are coupled to the respective first, second and third MTJ stacks.

15. A device comprising:
a substrate comprising circuit component disposed over a substrate surface;
an upper inter level dielectric (ILD) layer disposed over the substrate, wherein the upper ILD layer comprises a plurality of ILD levels; and
a plurality of magnetic tunneling junction (MTJ) stacks disposed in between adjacent ILD levels of the upper ILD layer, wherein the plurality of the MTJ stacks comprise
a first MTJ stack having a first free layer, a first tunneling barrier layer and a first fixed layer, wherein the first free layer is perpendicular to the first tunneling layer and fixed layer in the plane of the substrate surface, and
a second MTJ stack having a second free layer, a second tunneling barrier layer and a second fixed layer, wherein the first free layer is perpendicular to the second free layer in the plane of the substrate surface.

16. The device of claim 15 , wherein
the first free layer comprises a first long axis and a first short axis;
the second free layer comprises a second long axis and a second short axis; and
the first long axis is aligned with the second short axis and the first short axis is aligned with the second long axis.

17. The device of claim 15 further comprising a third MTJ stack having a third free layer, a third tunneling barrier layer and a third fixed layer.

18. The device of claim 17 wherein the second free layer has a first aspect ratio and the third free layer has a second aspect ratio.

19. The device of claim 15 wherein the first MTJ stack and the second MTJ stack have similar thicknesses.

20. The device of claim 18 wherein the first aspect ratio is different from the second aspect ratio.

Assignees

• Globalfoundries Sg Pte Ltd

Inventors

• Wang Chenchen Jacob
• Quek Kiok Boone Elgin

Classifications

• H01L43/12 Primary

  Electricity · mapped topic

• H01L27/228

  Electricity · mapped topic

• H01L43/08

  Electricity · mapped topic

• H10B61/22 Primary

  of the field-effect transistor [FET] type · CPC title

• H10N50/01 Primary

  Manufacture or treatment · CPC title