Semiconductor device and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-9660102-B2
Application number	US-201514679144-A
Country	US
Kind code	B2
Filing date	Apr 6, 2015
Priority date	Feb 27, 2009
Publication date	May 23, 2017
Grant date	May 23, 2017

Abstract

An object is to reduce to reduce variation in threshold voltage to stabilize electric characteristics of thin film transistors each using an oxide semiconductor layer. An object is to reduce an off current. The thin film transistor using an oxide semiconductor layer is formed by stacking an oxide semiconductor layer containing insulating oxide over the oxide semiconductor layer so that the oxide semiconductor layer and source and drain electrode layers are in contact with each other with the oxide semiconductor layer containing insulating oxide interposed therebetween; whereby, variation in threshold voltage of the thin film transistors can be reduced and thus the electric characteristics can be stabilized. Further, an off current can be reduced.

First claim

What is claimed is:

1. A semiconductor device comprising:
a gate electrode layer;
a gate insulating layer;
an oxide semiconductor layer comprising a channel formation region adjacent to the gate electrode layer with the gate insulating layer therebetween, the oxide semiconductor layer including indium and oxygen; and
source and drain electrode layers electrically connected to the oxide semiconductor layer,
wherein the channel formation region includes a crystal grain which is 1 nm to 10 nm in diameter.

2. A semiconductor device comprising:
a gate electrode layer;
a gate insulating layer;
an oxide semiconductor layer comprising a channel formation region adjacent to the gate electrode layer with the gate insulating layer therebetween, the oxide semiconductor layer including indium and oxygen; and
source and drain electrode layers electrically connected to the oxide semiconductor layer,
wherein the oxide semiconductor layer has an amorphous structure, and
wherein the channel formation region includes a crystal grain which is 1 nm to 10 nm in diameter.

3. A semiconductor device comprising:
a gate electrode layer;
a gate insulating layer;
a first oxide semiconductor layer comprising a channel formation region and a second oxide semiconductor layer adjacent to the gate electrode layer with the gate insulating layer therebetween, each of the first oxide semiconductor layer and the second oxide semiconductor layer including indium and oxygen; and
source and drain electrode layers electrically connected to the second oxide semiconductor layer,
wherein a conductance of the first oxide semiconductor layer is higher than that of the second oxide semiconductor layer, and
wherein the channel formation region includes a crystal grain which is 1 nm to 10 nm in diameter.

4. A semiconductor device comprising:
a gate electrode layer;
a gate insulating layer;
a first oxide semiconductor layer comprising a channel formation region and a second oxide semiconductor layer adjacent to the gate electrode layer with the gate insulating layer therebetween, each of the first oxide semiconductor layer and the second oxide semiconductor layer including indium and oxygen; and
source and drain electrode layers electrically connected to the second oxide semiconductor layer,
wherein a conductance of the first oxide semiconductor layer is higher than that of the second oxide semiconductor layer,
wherein the first oxide semiconductor layer has an amorphous structure, and
wherein the channel formation region includes a crystal grain which is 1 nm to 10 nm in diameter.

5. The semiconductor device according to claim 1 , wherein the oxide semiconductor layer is over the gate electrode layer.

6. The semiconductor device according to claim 1 , wherein the oxide semiconductor layer comprises gallium and zinc.

7. The semiconductor device according to claim 1 , wherein the source and drain electrode layers comprise a material selected from aluminum, copper, molybdenum, titanium, chromium, tantalum, tungsten, neodymium, and scandium, an alloy material thereof, or a nitride thereof.

8. The semiconductor device according to claim 1 , further comprising an insulating layer over the source and drain electrode layers,
wherein the oxide semiconductor layer is over the gate electrode layer, and
wherein the insulating layer is in contact with an upper surface of the oxide semiconductor layer between the source and drain electrode layers.

9. The semiconductor device according to claim 1 , further comprising an insulating layer over at least the channel formation region of the oxide semiconductor layer,
wherein the oxide semiconductor layer is over the gate electrode layer, and
wherein the source and drain electrode layers are formed over the insulating layer.

10. The semiconductor device according to claim 2 , wherein the oxide semiconductor layer is over the gate electrode layer.

11. The semiconductor device according to claim 2 , wherein the oxide semiconductor layer comprises gallium and zinc.

12. The semiconductor device according to claim 2 , wherein the source and drain electrode layers comprise a material selected from aluminum, copper, molybdenum, titanium, chromium, tantalum, tungsten, neodymium, and scandium, an alloy material thereof, or a nitride thereof.

13. The semiconductor device according to claim 2 , further comprising an insulating layer over the source and drain electrode layers,
wherein the oxide semiconductor layer is over the gate electrode layer, and
wherein the insulating layer is in contact with an upper surface of the oxide semiconductor layer between the source and drain electrode layers.

14. The semiconductor device according to claim 2 , further comprising an insulating layer over at least the channel formation region of the oxide semiconductor layer,
wherein the oxide semiconductor layer is over the gate electrode layer, and
wherein the source and drain electrode layers are formed over the insulating layer.

15. The semiconductor device according to claim 3 , wherein the first oxide semiconductor layer is over the gate electrode layer.

16. The semiconductor device according to claim 3 , wherein the first oxide semiconductor layer comprises gallium and zinc.

17. The semiconductor device according to claim 3 , wherein the source and drain electrode layers comprise a material selected from aluminum, copper, molybdenum, titanium, chromium, tantalum, tungsten, neodymium, and scandium, an alloy material thereof, or a nitride thereof.

18. The semiconductor device according to claim 3 , further comprising an insulating layer over the source and drain electrode layers,
wherein the first oxide semiconductor layer is over the gate electrode layer, and
wherein the insulating layer is in contact with an upper surface of the second oxide semiconductor layer between the source and drain electrode layers.

19. The semiconductor device according to claim 3 , further comprising an insulating layer over at least the channel formation region,
wherein the first oxide semiconductor layer is over the gate electrode layer, and
wherein the source and drain electrode layers are formed over the insulating layer.

20. The semiconductor device according to claim 4 , wherein the first oxide semiconductor layer is over the gate electrode layer.

21. The semiconductor device according to claim 4 , wherein the first oxide semiconductor layer comprises gallium and zinc.

22. The semiconductor device according to claim 4 , wherein the source and drain electrode layers comprise a material selected from aluminum, copper, molybdenum, titanium, chromium, tantalum, tungsten, neodymium, and scandium, an alloy material thereof, or a nitride thereof.

23. The semiconductor device according to claim 4 , further comprising an insulating layer over the source and drain electrode layers,
wherein the first oxide semiconductor layer is over the gate electrode layer, and
wherein the insulating layer is in contact with an upper surface of the second oxide semiconductor layer between the source and drain electrode layers.

24. The semiconductor device according to claim 4 , further comprising an insulating layer over at least the channel formation region,
wherein the first oxide semiconductor layer is over the gate electrode layer, and
wherein the source and drain electrode layers are formed over the insulating layer.

Assignees

• Semiconductor Energy Lab

Inventors

• Godo Hiromichi
• Akimoto Kengo
• Yamazaki Shunpei

Classifications

• H10P14/3441

  Conductivity type · CPC title

• H10P14/3434

  being oxide semiconductor materials (Group IIB-VIA semiconductor materials H10P14/3424) · CPC title

• H10P14/3426

  Oxides · CPC title

• H10P14/22

  using physical deposition, e.g. vacuum deposition or sputtering · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title