Non-volatile memory devices with vertically integrated capacitor electrodes

Patent metadata

Field	Value
Publication number	US-9659954-B2
Application number	US-201514702038-A
Country	US
Kind code	B2
Filing date	May 1, 2015
Priority date	May 2, 2014
Publication date	May 23, 2017
Grant date	May 23, 2017

Abstract

Provided is a vertical non-volatile memory device in which a capacitor constituting a peripheral circuit region is formed as a vertical type so that an area occupied by the capacitor in the entire device can be reduced as compared with a planar capacitor. Thus, a non-volatile memory device may be highly integrated and have a high capacity. The device includes a substrate having a cell region and a peripheral circuit region, a memory cell string including a plurality of vertical memory cells formed in the cell region and channel holes formed to penetrate the vertical memory cells in a first direction vertical to the substrate, an insulating layer formed in the peripheral circuit region on the substrates at substantially the same level as an upper surface of the memory cell string, and a plurality of capacitor electrodes formed on the peripheral circuit region to penetrate at least a portion of the insulating layer in the first direction, the plurality of capacitor electrodes extending parallel to the channel holes. The plurality of capacitor electrodes are spaced apart from one another in a second direction parallel to the substrate, and the insulating layer is interposed between a pair of adjacent capacitor electrodes from among the plurality of capacitor electrodes.

First claim

What is claimed is:

1. A nonvolatile memory device, comprising:
a plurality of spaced-apart strings of vertically arranged nonvolatile memory cells on a memory cell region of a substrate;
channel regions vertically extending through the plurality of spaced-apart strings;
an electrically insulating layer on a peripheral circuit region of the substrate, which extends adjacent the memory cell region;
a plurality of spaced-apart first capacitor electrodes on the peripheral circuit region, said first capacitor electrodes extending vertically and at least partially through said electrically insulating layer in a direction parallel to the channel regions in said plurality of spaced-apart strings of vertically arranged nonvolatile memory cells; and
a trench insulating layer embedded within the peripheral circuit region of the substrate;
wherein the plurality of spaced-apart first capacitor electrodes extend through said electrically insulating layer and into a portion of the trench insulating layer extending below the surface of the substrate.

2. The device of claim 1 , wherein the trench insulating layer operates as an additional capacitor dielectric region, which extends between each of the first capacitor electrodes and an underlying portion of the substrate.

3. The device of claim 1 , wherein a pitch between a plurality of the vertically extending channel regions is equivalent to a pitch between a plurality of the plurality of spaced-apart first capacitor electrodes.

4. A non-volatile memory device comprising:
a substrate having a cell region and a peripheral circuit region;
a memory cell string including a plurality of vertical memory cells formed in the cell region and channel holes formed to penetrate the vertical memory cells in a first direction vertical to the substrate;
an insulating layer formed in the peripheral circuit region on the substrates at substantially the same level as an upper surface of the memory cell string; and
a plurality of capacitor electrodes formed on the peripheral circuit region to penetrate at least a portion of the insulating layer in the first direction, the plurality of capacitor electrodes extending parallel to the channel holes;
wherein the plurality of capacitor electrodes are spaced apart from one another in a second direction parallel to the substrate, and the insulating layer is interposed between a pair of adjacent capacitor electrodes from among the plurality of capacitor electrodes; and
wherein upper surfaces of the plurality of capacitor electrodes are at substantially the same level as an upper surface of the insulating layer.

5. The device of claim 4 , wherein the plurality of capacitor electrodes are formed on the substrate to penetrate the insulating layer in the first direction, and lower surfaces of the plurality of capacitor electrodes are at a lower level than an uppermost surface of the substrate.

6. The device of claim 4 , further comprising a lower insulating layer formed on the substrate in the peripheral circuit region,
wherein the plurality of capacitor electrodes are formed on the lower insulating layer, and
lower surfaces of the plurality of capacitor electrodes are at a higher level than an upper surface of the substrate.

7. The device of claim 4 , further comprising a trench oxide layer formed in the substrate,
wherein the plurality of capacitor electrodes are formed on the trench oxide layer.

8. The device of claim 4 , further comprising a plurality of dummy gate structures formed on the substrate in the peripheral circuit region,
wherein the plurality of capacitor electrodes are formed on the plurality of dummy gate structures.

9. The device of claim 4 , wherein each of the plurality of capacitor electrodes has a circular pillar shape extending in the first direction.

10. The device of claim 9 , wherein a lower surface of each of the plurality of capacitor electrodes has substantially the same planar area as each of the channel holes.

11. The device of claim 4 , wherein each of the plurality of capacitor electrodes has a pillar shape having an elliptical lower surface.

12. The device of claim 4 , wherein each of the plurality of capacitor electrodes has a pillar shape having a polygonal lower surface.

13. The device of claim 4 ,
wherein each of the plurality of capacitor electrodes is separated from the surface of the substrate by a corresponding electrically conductive gate member, which is separated from the surface of the substrate by a lower electrically insulating layer.

14. A non-volatile memory device comprising:
a substrate having a cell region and a peripheral circuit region;
a memory cell string including a plurality of memory cells stacked in the cell region on the substrate;
a lower insulating layer formed in the peripheral circuit region on the substrate;
an upper insulating layer formed on the lower insulating layer and having an upper surface disposed at substantially the same level as an upper surface of the memory cell string; and
a plurality of vertical capacitors formed in via holes penetrating the upper insulating layer in a vertical direction to the substrate,
wherein each of the plurality of vertical capacitors comprises:
a first capacitor electrode formed along an inner wall of the via hole;
a second capacitor electrode surrounded with the first capacitor electrode in the via hole to fill the via hole; and
a capacitor insulating layer interposed between the first capacitor electrode and the second capacitor electrode,
wherein the plurality of vertical capacitors are formed a sufficiently close distance apart from one another and extend parallel to one another such that charges are accumulated in the upper insulating layer interposed between a pair of adjacent vertical capacitors from among the plurality of vertical capacitors.

15. The device of claim 14 , wherein each of the plurality of vertical capacitors has a cylindrical structure, and
the second capacitor electrode includes a lower surface having a concentric circular shape with the same center as the via hole, and has a circular pillar shape extending in a direction vertical to an upper surface of the substrate.

16. The device of claim 14 , wherein the second capacitor electrode has an elliptical pillar shape, which has an elliptical lower surface in a direction parallel to an upper surface of the substrate and extends in a direction vertical to an upper surface of the substrate.

17. The device of claim 14 , wherein each of the plurality of vertical capacitors has a square pillar shape, which has a square lower surface and extends in a direction vertical to an upper surface of the substrate.

18. The device of claim 14 , wherein each of the plurality of vertical capacitors has a square pillar shape having a square lower surface, and
the plurality of vertical capacitors are arranged apart from one another in a first direction parallel to an upper surface of the substrate and in a second direction parallel to the upper surface of the substrate and perpendicular to the first direction.

Assignees

• Kim Hyun-Suk
• Lee Joon-Hee
• Rho Kee-Jeong
• Samsung Electronics Co Ltd

Inventors

• Kim Hyun-Suk
• Lee Joon-Hee
• Rho Kee-Jeong

Classifications

• H01L27/11556

  Electricity · mapped topic

• H01L27/11565

  Electricity · mapped topic

• H01L28/60

  Electricity · mapped topic

• H01L27/1157

  Electricity · mapped topic

• H01L28/91

  Electricity · mapped topic