Manufacturing method for semiconductor device and semiconductor device

Patent metadata

Field	Value
Publication number	US-9659872-B2
Application number	US-201514977130-A
Country	US
Kind code	B2
Filing date	Dec 21, 2015
Priority date	May 31, 2012
Publication date	May 23, 2017
Grant date	May 23, 2017

Abstract

A step of forming a connecting member configured to electrically connect a first conductive line and a second conductive line includes a phase of perforating a laminate from a first semiconductor wafer to form a plurality of connection holes that reach the second conductive line and a phase of filling the plurality of penetrating connection holes with a conductive material to form conductive sections in contact with the second conductive line.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first semiconductor substrate;
a second semiconductor substrate;
a first pattern which is included in a first metal layer arranged between the first semiconductor substrate and the second semiconductor substrate;
a second pattern which is included in a second metal layer arranged between the first semiconductor substrate and the second semiconductor substrate; and
conductive sections which penetrate through the first semiconductor substrate,
wherein at least two of the conductive sections are in contact with the second pattern, and the second pattern is electrically connected with the first pattern via the at least two of the conductive sections in contact with the second pattern.

2. A semiconductor device comprising:
a first semiconductor substrate;
a second semiconductor substrate;
a first wiring section arranged between the first semiconductor substrate and the second semiconductor substrate;
a second wiring section arranged between the first semiconductor substrate and the second semiconductor substrate; and
one conductive line of conductive lines comprises the first wiring section, the second wiring section, and a plurality of conductive sections electrically connecting the first wiring section and the second wiring section, and
wherein the conductive sections penetrate through the first semiconductor substrate and are in contact with the second wiring section.

3. The semiconductor device according to claim 2 , wherein the one conductive line comprises another conductive sections electrically connecting the first wiring section and the second wiring section, and the another conductive sections penetrate through the first semiconductor substrate and are in contact with the first wiring section.

4. The semiconductor device according to claim 1 , wherein a straight line which connects two of the conductive sections in contact with the second pattern intersects with a straight line which connects two of the conductive sections in contact with the first pattern.

5. An electronic apparatus comprising:
the semiconductor device according to claim 1 ; and
a display device configured to display an image based on a signal obtained from the semiconductor device.

6. The semiconductor device according to claim 1 , wherein the at least two of the conductive sections are in contact with the first pattern, and the first pattern is electrically connected with the second pattern via the at least two conductive sections in contact with the first pattern.

7. The semiconductor device according to claim 6 , wherein a part of the second pattern is arranged between the first pattern and the second semiconductor substrate.

8. The semiconductor device according to claim 6 , wherein the at least two of the conductive sections in contact with the first pattern is provided outside a straight line which connects the at least two of the conductive sections in contact with the second pattern.

9. The semiconductor device according to claim 6 , wherein the at least two of the conductive sections in contact with the first pattern, is not in contact with the second pattern.

10. The semiconductor device according to claim 1 , wherein a distance between the second metal layer and the first semiconductor substrate is larger than a distance between the second metal layer and the first semiconductor substrate.

11. The semiconductor device according to claim 10 , wherein a thickness of the first semiconductor substrate is, not more than 10 um.

12. The semiconductor device according to claim 11 , wherein the first semiconductor substrate has a photoelectric conversion element, and the second semiconductor substrate has a semiconductor element, and the second pattern is electrically connected to the semiconductor element via metal layers.

13. The semiconductor device according to claim 12 , wherein the first pattern is electrically connected to an electrode pad.

14. The semiconductor device according to claim 12 , wherein
the first semiconductor substrate includes an image sensing region in which pixels arrayed in rows and columns,
the second semiconductor substrate includes a signal processing region which processes a signal obtained by the image sensing region,
signals output from the columns of the pixels are transferred in parallel to the signal processing region through a plurality of conductive lines, and
one of the plurality of conductive lines comprises the first pattern, the second pattern and the at least two of the conductive sections in contact with the second pattern.

15. The semiconductor device according to claim 2 , wherein the first wiring section is connected to a semiconductor element provided on the first semiconductor substrate.

16. The semiconductor device according to claim 2 , wherein the plurality of conductive sections are in contact with the first wiring section.

17. The semiconductor device according to claim 2 , wherein the conductive sections are connected by a coupling conductive section arranged on the first semiconductor substrate on a side opposite to the second semiconductor substrate.

18. The semiconductor device according to claim 2 , wherein the one conductive line is electrically discontinuous from another conductive line of the conductive lines in the semiconductor device by an insulator section of a wiring structure between the first semiconductor substrate and the second semiconductor substrate or by a semiconductor section of the second semiconductor substrate.

19. The semiconductor device according to claim 2 , wherein another conductive line of the conductive lines electrically connects a semiconductor element provided on the first semiconductor substrate and a semiconductor element provided on the second semiconductor substrate via a connecting member, and the connecting member comprises more than three conductive sections that penetrate through the first semiconductor substrate.

20. The semiconductor device according to claim 2 , wherein the first semiconductor substrate has an array of photoelectric conversion elements.

21. The semiconductor device according to claim 2 , wherein
the first semiconductor substrate includes an image sensing region in which pixels arrayed in rows and columns,
the second semiconductor substrate includes a signal processing region which processes a signal obtained by the image sensing region,
signals output from the columns of the pixels are transferred in parallel to the signal processing region through a plurality of conductive lines, and
the one conductive line is included in the plurality of conductive lines.

22. The semiconductor device according to claim 2 , wherein the second wiring section includes a plurality of metal layers electrically connected to each other, and a distance between the second wiring section and the first semiconductor substrate is larger than a distance between the first wiring section and the first semiconductor substrate.

23. The semiconductor device according to claim 22 , wherein the first wiring sections include a plurality of metal layers connected to each other.

24. The semiconductor device according to claim 2 , wherein a thickness of the first semiconductor substrate is, not more than 10 um.

25. The semiconductor device according to claim 24 , wherein a primary material of the plurality of conductive sections are copper or tungsten.

26. An el

Assignees

• Canon Kk

Inventors

• Kumano Hideomi

Classifications

• H10W20/217

  comprising ring-shaped isolation structures outside of the via holes · CPC title

• H10W20/2134

  TSVs extending from the semiconductor wafer into back-end-of-line layers · CPC title

• H10W20/0253

  comprising forming the through-semiconductor vias after stacking of the chips, wafers or substrates · CPC title

• H10W20/0242

  comprising etching via holes from the back sides of the chips, wafers or substrates · CPC title

• H10W20/0234

  comprising etching via holes that stop on pads or on electrodes · CPC title