Methods of fabricating semiconductor devices and structures thereof

Patent metadata

Field	Value
Publication number	US-9659778-B2
Application number	US-201514744781-A
Country	US
Kind code	B2
Filing date	Jun 19, 2015
Priority date	Dec 22, 2008
Publication date	May 23, 2017
Grant date	May 23, 2017

Abstract

Methods of fabricating semiconductor devices and structures thereof are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a gate material stack over a substrate having a first region and a second region. The gate material stack includes a semiconductive gate material. A thickness is altered or a substance is introduced to the semiconductive gate material in the first region or the second region of the substrate. The gate material stack is patterned in the first region and the second region resulting in a first transistor in the first region of the substrate comprising an NMOS FET of a CMOS device and a second transistor in the second region of the substrate comprising an NMOS FET of the CMOS device. The first transistor has a first threshold voltage and the second transistor has a second threshold voltage different than the first threshold voltage.

First claim

What is claimed is:

1. A method of manufacturing a CMOS device, the method comprising:
forming a gate material stack over a substrate comprising a first region, a second region, and a third region, the gate material stack including a semiconductive gate material;
patterning the gate material stack in the first region and the second region;
modifying the semiconductive gate material of the gate material stack in the first region or the second region of the substrate by introducing a substance comprising N, C, In, Fl, or Cl, to the semiconductive gate material using a first process;
modifying the semiconductive gate material of the gate material stack in the third region of the substrate by introducing a substance comprising N, C, In, Fl, or Cl, to the semiconductive gate material using a second process different from the first process; and
forming a first transistor in the first region of the substrate, a second transistor in the second region of the substrate, and a third transistor in the third region of the substrate, wherein the first, the second, and the third transistors are all NMOS transistors or all PMOS transistors, wherein the first transistor has a first threshold voltage, the second transistor has a second threshold voltage, the third transistor has a third threshold voltage, wherein the first threshold voltage, the second threshold voltage, and the third threshold voltage are different from each other.

2. The method according to claim 1 , further comprising:
patterning the gate material stack in the third region; and.

3. The method according to claim 2 , wherein the third transistor in the third region of the substrate comprises an NMOS FET of the CMOS device.

4. The method according to claim 3 , further comprising forming a plurality of additional transistors on the substrate, wherein the additional transistors have the third threshold voltage.

5. The method according to claim 1 , wherein introducing a substance comprises using an implantation process, a plasma process, or an in-situ doping process.

6. The method according to claim 1 , wherein forming the gate material stack comprises forming a gate dielectric material, forming a metal gate material over the gate dielectric material, and forming the semiconductive gate material over the metal gate material.

7. The method according to claim 6 , wherein forming the gate material stack further comprises forming an interfacial layer over the substrate before forming the gate dielectric material.

8. The method according to claim 7 , further comprising modifying at least one of the gate dielectric material, the metal gate material, and the interfacial layer.

9. The method according to claim 6 , wherein forming the gate material stack further comprises forming a cap layer over the gate dielectric material before forming the metal gate material.

10. The method according to claim 9 , further comprising patterning the cap layer.

11. The method according to claim 9 , further comprising introducing the substance into at least a portion of the cap layer.

12. A method of manufacturing a CMOS device, the method comprising:
forming a gate material stack over a substrate comprising a first region and a second region, the gate material stack including a silicon dioxide layer over the substrate, a high-k dielectric material layer over the silicon dioxide layer, a cap layer comprising a different oxide than the silicon dioxide layer and the high-k dielectric material, a metal gate material layer over the cap layer, and a semiconductive gate material over the metal gate material layer;
patterning the gate material stack in the first region and the second region;
introducing a substance comprising N, C, In, Fl, or Cl to the semiconductive gate material using a plasma process or an in-situ doping process; and
forming a first transistor in the first region of the substrate and a second transistor in the second region of the substrate, wherein the first transistor and the second transistor form part of the CMOS device.

13. The method according to claim 12 , wherein forming the gate material stack comprises forming the high-k dielectric material layer, forming a metal gate material layer over the high-k dielectric material layer, and forming the semiconductive gate material over the metal gate material layer.

14. The method according to claim 13 , wherein forming the gate material stack further comprises forming the silicon dioxide layer over the substrate before forming the high-k dielectric material layer.

15. The method according to claim 14 , further comprising modifying at least one of the high-k dielectric material layer, the metal gate material layer, and the silicon dioxide layer.

16. The method according to claim 13 , wherein forming the gate material stack further comprises forming the cap layer over the high-k dielectric material layer before forming the metal gate material layer.

17. The method according to claim 16 , further comprising patterning the cap layer.

18. The method according to claim 16 , further comprising introducing the substance into at least a portion of the cap layer.

19. The method according to claim 12 , wherein introducing the substance comprises using the in-situ doping process.

20. The method according to claim 12 , wherein introducing the substance comprises using the plasma process.

21. A method of manufacturing a CMOS device, the method comprising:
providing a substrate comprising a first region and a second region;
forming a gate material stack over the first region and the second region, the gate material stack including a silicon dioxide layer over the substrate, a high-k dielectric material layer over the silicon dioxide layer, a cap layer comprising a different oxide than the silicon dioxide layer and the high-k dielectric material, a metal gate material layer over the cap layer, and a semiconductive gate material over the metal gate material layer;
forming a first gate stack and a second gate stack by patterning the gate material stack in the first region and the second region;
masking the first gate stack while exposing the second gate stack;
using a plasma process, introducing a substance comprising N, C, In, Fl, or Cl to the semiconductive gate material of the second gate stack while masking the first gate stack and exposing the second gate stack; and
forming a first transistor in the first region of the substrate and a second transistor in the second region of the substrate, wherein the first transistor and the second transistor are a same type of transistor with different threshold voltages.

22. The method according to claim 21 , wherein forming the gate material stack comprises forming the high-k dielectric material layer, forming metal gate material layer over the high-k dielectric material, and forming the semiconductive gate material over the metal gate material.

23. The method according to claim 22 , wherein forming the gate material stack further comprises forming the silicon dioxide layer over the substrate before forming the high-k dielectric material layer.

24. The method according to claim 22 , wherein forming the gate material stack further comprises:
forming the cap layer over the high-k dielectric material layer before forming the metal gate material layer; and
patterning the cap layer while patterning the gate material stack.

25. The method according to claim 24 , further comprising introducing the sub

Assignees

• Infineon Technologies Ag

Inventors

• Stahrenberg Knut
• Han Jin-Ping

Classifications

• H10D64/01348

  with substrate doping, e.g. N, Ge or C implantation, before formation of the insulator · CPC title

• H10D64/0135

  by deposition of a layer, e.g. metal, metal compound or polysilicon, followed by transformation thereof into the insulator · CPC title

• H10D64/01318 Primary

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314) · CPC title

• H01L29/518

  Electricity · mapped topic

• H01L21/2822

  Electricity · mapped topic