Gate driving unit and display device having the same

Patent metadata

Field	Value
Publication number	US-9659542-B2
Application number	US-23011205-A
Country	US
Kind code	B2
Filing date	Sep 19, 2005
Priority date	Sep 18, 2004
Publication date	May 23, 2017
Grant date	May 23, 2017

Abstract

A gate driver includes multiple stages. Each stage has a circuit portion and a wiring portion. The wiring portion delivers first and second clock signals to the circuit portion. Further, the wiring portion includes first and second clock wirings receiving the first and second clock signal, respectively, first connecting wirings electrically connecting the first clock wiring with a first every other stage, and second connecting wirings electrically connecting the second clock wiring with the odd-numbered stages. Further, the wiring portion includes third connecting wirings electrically connecting the first connecting wiring with a second every other stage and fourth connecting wirings electrically connecting the second connecting wiring with the even-numbered stages. This configuration may prevent the gate driver from operating erroneously and reduce power consumed by the gate driver.

First claim

What is claimed is:

1. A driving unit comprising:
a circuit portion, the circuit portion comprises a plurality of stages comprising a first every other stage and a second every other stage different from the first every other stage, the plurality of stages generate output signals according to at least one of first and second clocks; and
a wiring portion, the wiring portion delivers control signals to the circuit portion, the wiring portion comprises:
first and second clock wirings, the first and second clock wirings deliver the first and second clock, respectively;
first connecting wirings, the first connecting wirings connect the first clock wiring with the first every other stage;
second connecting wirings, the second connecting wirings connect the second clock wiring with the second every other stage;
third connecting wirings, the third connecting wirings extend independent of first clock wiring and directly connect the first connecting wirings with the second every other stage; and
fourth connecting wirings, the fourth connecting wirings extend independent of the second clock wiring and directly connect the second connecting wirings with the first every other stage.

2. The driving unit of claim 1 , wherein the second every other stage is even-numbered stages of the plurality of stages, and the first every other stage is odd-numbered stages of the plurality of stages.

3. The driving unit of claim 2 , wherein the wiring portion further comprises a start signal wiring, the start signal wiring delivers a vertical synchronization start signal to a first stage of the plurality of stages.

4. The driving unit of claim 3 , wherein the wiring portion further comprises a fifth connecting wiring, the fifth connecting wiring delivers the second clock to a second clock terminal of a last stage of the plurality of stages.

5. The driving unit of claim 4 , wherein the wiring portion further comprises a reset wiring and sixth connecting wirings, the reset wiring delivers an output signal of the last stage to reset terminals of the even-numbered or the odd-numbered stages and the sixth connecting wirings deliver an off voltage to voltage terminals of the plurality of stages.

6. The driving unit of claim 5 , wherein the start signal wiring delivers the vertical synchronization start signal to the last stage.

7. The driving unit of claim 1 , wherein the first and second clock wirings and third and fourth connecting wirings are formed on a first layer, respectively, and the first and second connecting wirings are formed on a second layer, respectively.

8. The driving unit of claim 7 , further comprising first and second contact electrodes, the first contact electrodes electrically connect the first clock wiring with the first connecting wiring, and the second contact electrodes electrically connect the second clock wiring with the second connecting wiring.

9. The driving unit of claim 7 , further comprising third and fourth contact electrodes, the third contact electrodes electrically connect the third connecting wirings with the first connecting wirings, and the fourth contact electrodes electrically connect the fourth connecting wirings with the second connecting wirings.

10. A display device, comprising:
a display panel, the display panel displays images in response to gate and data signals;
a data driver, the data driver supplies the data signals to the display panel; and
a gate driver, the gate driver supplies the gate signals to the display panel and comprises:
a circuit portion, the circuit portion comprises a plurality of stages comprising a first every other stage and a second every other stage different from the first every other stage, the plurality of stages generate output signals according to at least one of first and second clocks; and
a wiring portion, the wiring portion delivers control signals to the circuit portion, the wiring portion comprises:
first and second clock wirings, the first and second clock wirings deliver the first and second clock, respectively;
first connecting wirings, the first connecting wirings connect the first clock wiring with the first every other stage;
second connecting wirings, the second connecting wirings connect the second clock wiring with the second every other stage;
third connecting wirings, the third connecting wirings extend independent of the first clock wiring and directly connect the first connecting wirings with the second every other stage; and
fourth connecting wirings, the fourth connecting wirings extend independent of the second clock wiring and directly connect the second connecting wirings with the first every other stage.

11. The display device of claim 10 , wherein the gate driver is formed on the display panel.

12. The display device of claim 10 , wherein the display panel comprises:
a first display substrate, the first display substrate comprises the gate driver, gate lines, and data lines;
a second display substrate, the second display substrate is opposed to the first display substrate; and
a liquid crystal layer, the liquid crystal layer is disposed between the first and second substrates.

Assignees

• Park Haeng-Won
• Moon Seung-Hwan
• Kang Nam-Soo
• Moon Sung-Jae
• Kim Sung-Man
• Lee Seong-Young
• Lee Yong-Soon
• Samsung Display Co Ltd

Inventors

• Park Haeng-Won
• Moon Seung-Hwan
• Kang Nam-Soo
• Moon Sung-Jae
• Kim Sung-Man
• Lee Seong-Young
• Lee Yong-Soon

Classifications

• G09G3/3677 Primary

  suitable for active matrices only · CPC title

• G09G2300/0426

  Layout of electrodes and connections · CPC title

• G11C19/184

  with field-effect transistors, e.g. MOS-FET · CPC title

• G02F1/133 Primary

  Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements (arrangements or circuits for control of liquid crystal elements in a matrix, not structurally associated with these elements G09G3/36) · CPC title

• G09G3/36

  using liquid crystals · CPC title