Mid command buffer preemption for graphics workloads

Patent metadata

Field	Value
Publication number	US-9659342-B2
Application number	US-201313931915-A
Country	US
Kind code	B2
Filing date	Jun 29, 2013
Priority date	Jun 29, 2013
Publication date	May 23, 2017
Grant date	May 23, 2017

Abstract

Mid-command buffer preemption is described for graphics workloads in a graphics processing environment. In one example, instructions of a first context are executed at a graphics processor, the first context has a sequence of instructions in an addressable buffer and at least one of the instructions is a preemption instruction. Upon executing the preemption instruction, execution of the first context is stopped before the sequence of instructions is completed. An address is stored for an instruction with which the first context will be resumed. The second context is executed, and upon completion of the execution of the second context, the execution of the first context is resumed at the stored address.

First claim

What is claimed is:

1. A method comprising:
setting a valid address in a pointer register to a buffer location by a scheduler, the addressed buffer location being a start of an instruction sequence of a second context;
executing instructions of a first context at a graphics processor and incrementing a head pointer after the execution of each instruction, the head pointer indicating the location of a next instruction to be executed, the context having a sequence of instructions in a first addressable buffer, at least one of the instructions being a preemption instruction, the preemption instruction having a reference to the address in the pointer register that was set by the scheduler;
updating the head pointer based on the address in the pointer register;
upon executing the preemption instruction, stopping execution of the first context before the sequence of instructions is completed;
storing an address for an instruction with which the first context will be resumed;
executing the second context at the graphics processor based on the updated head pointer; and
upon completion of the execution of the second context, resuming the execution of the first context at the stored address and updating the head pointer based on the stored address.

2. The method of claim 1 , wherein said resuming the execution of the first context comprises:
executing a start command indicating an address offset; and
resuming execution at the address of the start command plus the address offset.

3. The method of claim 1 , wherein the preemption instruction includes a reference to a start address for the second context.

4. The method of claim 1 , further comprising:
checking the pointer register during the execution of the first context; and
jumping to an address indicated by the pointer register, the address corresponding to a location of a first instruction of the second context.

5. The method of claim 4 , further comprising:
checking the pointer register during the execution of the first context;
jumping to an address indicated by the pointer register, the address indicating a first instruction of the second context; and
executing the instructions of the second context from the first instruction to an end command in the instructions of the second context.

6. The method of claim 1 , wherein the second context is stored in a second addressable buffer in the form of a ring buffer, wherein said executing a second context comprises executing the instructions in the second addressable buffer, and wherein said resuming execution of the first context comprises executing instructions in the first addressable buffer in the form of a batch buffer.

7. The method of claim 6 , wherein the preemption instruction includes an address in the second addressable buffer corresponding to the first instruction of the second context in the second addressable buffer.

8. The method of claim 6 , further comprising executing an end instruction in the second addressable buffer and wherein said resuming execution is performed in response to executing the end instruction.

9. The method of claim 1 , wherein the instructions of the first context are executed from a ring buffer, the method further comprising receiving a preemption command to execute the second context before stopping execution of the first context, the preemption command indicating whether the second context is in the ring buffer or in a separate batch buffer.

10. The method of claim 1 , wherein said stopping execution further comprises storing the current state of the first context.

11. The method of claim 1 , wherein the graphics processor updates a head offset register upon executing an instruction of the first context, and wherein said storing an address comprises storing a current head offset register value.

12. The method of claim 11 , wherein the preemption instruction includes a reference to a pointer register for the second context, the pointer register indicating an address offset from a first instruction of a buffer containing the first context to the first instruction of the second context, the second context being contained in the first addressable buffer.

13. The method of claim 12 , wherein the pointer register is updated asynchronously.

14. A non-transitory computer-readable medium having instructions, that when executed by the computer, cause the computer to perform operations comprising:
setting a valid address in a pointer register to a buffer location by a scheduler, the addressed buffer location being a start of an instruction sequence of a second context;
executing instructions of a first context at a graphics processor by and incrementing a head pointer after the execution of each instruction, the head pointer indicating the location of a next instruction to be executed, the context having as sequence of instructions in as first addressable buffer, at least one of the instructions being a preemption instruction, the preemption instruction having a reference to the address in the pointer register that was set by the scheduling software;
updating the head pointer based on the address in the pointer register;
upon executing the preemption instruction stopping execution of the first context before the sequence of instructions is completed;
storm address for an instruction with which the first context will be resumed;
executing the second a second context at the graphics processor based on the updated head pointer; and
upon completion of the execution of the second context, resuming the execution of the first context at the stored address and updating the head pointer based on the stored address.

15. The medium of claim 14 , wherein said resuming the execution of the first context comprises:
executing a start command indicating an address offset; and
resuming execution at the address of the start command plus the address offset.

16. The medium of claim 14 , wherein the instructions of the first context are executed from a ring buffer, the instructions further comprising receiving a preemption command to execute the second context before stopping execution of the first context, the preemption command indicating whether the second context is in the ring buffer or in a separate batch buffer.

17. An apparatus comprising:
a graphics processor; and
an addressable graphics memory coupled to the graphics processor and incrementing a head pointer after the execution of each instruction, the head pointer indicating the location of a next instruction to be executed, the graphics memory having a ring buffer, a pointer register, and a register to store an address,
the graphics processor executing instructions of a first context, the context having a sequence of instructions in the ring buffer, at least one of the instructions being a preemption instruction, the preemption instruction having a reference to an address in a pointer register that was set by scheduling software, the address being a start of an instruction sequence of second context, updating the head pointer based on the address in the pointer register, upon executing the preemption instruction, stopping execution of the first context before the sequence of instructions is completed, storing an address for an instruction with which the first context will be resumed, executing the second context based on the updated head pointer, and upon completion of the execution of the second context, resuming the execution of the first context at the stored address and updating the head pointer based on the stored address.

18. The apparatus of claim 17 , the graphic

Assignees

• Nalluri Hema Chand
• Navale Aditya
• Ramadoss Murali
• Boles Jeffery S
• Intel Corp

Inventors

• Nalluri Hema Chand
• Navale Aditya
• Ramadoss Murali
• Boles Jeffery S

Classifications

• G06F9/485

  Task life-cycle, e.g. stopping, restarting, resuming execution (G06F9/4881 takes precedence) · CPC title

• G06T1/20

  Processor architectures; Processor configuration, e.g. pipelining · CPC title

• G06T1/60 Primary

  Memory management · CPC title

• G06F9/48

  Program initiating; Program switching, e.g. by interrupt · CPC title