Method and apparatus for synchronizing multiple MAC tables across multiple forwarding pipelines

Patent metadata

Field	Value
Publication number	US-9658984-B2
Application number	US-201414331971-A
Country	US
Kind code	B2
Filing date	Jul 15, 2014
Priority date	Jul 15, 2014
Publication date	May 23, 2017
Grant date	May 23, 2017

Abstract

Embodiments provide techniques for synchronizing forwarding tables across forwarding pipelines. One embodiment includes receiving, in a network switch comprising a plurality of forwarding pipelines, a plurality of data packets. Each of the plurality of data packets corresponds to a respective one of the plurality of forwarding pipelines. Each of the plurality of forwarding pipelines maintains a respective forwarding table corresponding to a respective plurality of ports managed by the forwarding pipeline. A plurality of update operations to be performed on the forwarding tables are determined, based on the received plurality of data packets. Embodiments further include performing the plurality of update operations on the forwarding tables, such that the forwarding tables across all forwarding pipelines of the plurality of forwarding pipelines are synchronized.

First claim

We claim:

1. A method, comprising:
receiving, in a network switch circuit comprising a plurality of forwarding pipelines, a plurality of data packets, wherein each of the plurality of data packets corresponds to a respective one of the plurality of forwarding pipelines, and wherein each of the plurality of forwarding pipelines contains a respective forwarding table corresponding to a respective plurality of ports managed by the forwarding pipeline;
based on the received plurality of data packets, determining a plurality of update operations to be performed on the forwarding tables; and
performing the plurality of update operations on the forwarding tables for each of the plurality of forwarding pipelines, such that all the forwarding tables across all forwarding pipelines of the plurality of forwarding pipelines are synchronized, thereby enabling updated information relating to the received plurality of data packets to be used by all forwarding pipelines of the plurality of forwarding pipelines, wherein performing the plurality of update operations for each of the plurality of forwarding pipelines further comprises:
determining that a first update operation and a second update operation of the plurality of update operations refer to a same memory bank of the forwarding tables, such that the first update operation and the second update operation are performed in serial and are not performed together in a single clock cycle;
selecting the first update operation to be performed on a current clock cycle;
performing the selected update operation on the current clock cycle; and
writing the second update operation to a write cache for execution on a subsequent clock cycle.

2. The method of claim 1 , further comprising:
maintaining the forwarding tables on each of the plurality of forwarding pipelines as a 4×4 D-left hash data structure in a memory of the forwarding pipeline.

3. The method of claim 2 , wherein the memory in a first one of the plurality of forwarding pipelines comprises a static random-access memory (SRAM) capable of performing a single read operation and a single write operation per clock cycle.

4. The method of claim 1 , wherein the forwarding table on each of the plurality of forwarding pipelines contains a global data set corresponding to all of the plurality of forwarding pipelines.

5. The method of claim 4 , wherein the forwarding tables on each of the plurality of forwarding pipelines are identical, wherein the forwarding tables provide a single logical routing table for all of the ports on the network switch.

6. The method of claim 1 , wherein the first update operation and the second update operation comprise forwarding table refresh operations.

7. An integrated circuit, comprising:
a plurality of ports;
a plurality of forwarding pipelines, wherein each of the plurality of forwarding pipelines is configured to manage a respective subset of the plurality of ports, and wherein each of the plurality of forwarding pipelines contains a respective forwarding table corresponding to the respective subset of the plurality of ports managed by the forwarding pipeline; and
logic circuit configured to:
receive a plurality of data packets on ports in the plurality of ports;
based on the received plurality of data packets, determine a plurality of update operations to be performed on the forwarding tables; and
perform the plurality of update operations on the forwarding tables for each of the plurality of forwarding pipelines, such that all the forwarding tables across all forwarding pipelines of the plurality of forwarding pipelines are synchronized, thereby enabling updated information relating to the received plurality of data packets to be used by all forwarding pipelines of the plurality of forwarding pipelines, wherein the logic circuit is further configured to:
determine that a first update operation and a second update operation of the plurality of update operations refer to a same memory bank of the forwarding tables, such that the first update operation and the second update operation are performed in serial and are not performed together in a single clock cycle;
select the first update operation to be performed on a current clock cycle;
perform the selected update operation on the current clock cycle; and
write the second update operation to a write cache for execution on a subsequent clock cycle.

8. The integrated circuit of claim 7 , wherein each of the plurality of forwarding pipelines further comprises a memory, and wherein each of the plurality of forwarding pipelines is configured to maintain the forwarding table as a 4×4 D-left hash data structure in a memory of the forwarding pipeline.

9. The integrated circuit of claim 8 , wherein the memory in a first one of the plurality of forwarding pipelines comprises a static random-access memory (SRAM) capable of performing a single read operation and a single write operation per clock cycle.

10. The integrated circuit of claim 7 , wherein the forwarding table on each of the plurality of forwarding pipelines contains a global data set corresponding to all of the plurality of forwarding pipelines.

11. The integrated circuit of claim 10 , wherein the forwarding tables on each of the plurality of forwarding pipelines are identical, wherein the forwarding tables provide a single logical routing table for all of the ports on the network switch.

12. The integrated circuit of claim 7 , wherein the first update operation and the second update operation comprise forwarding table refresh operations.

13. A network switch, comprising:
a plurality of ports;
a plurality of forwarding pipelines, wherein each of the plurality of forwarding pipelines is configured to manage a respective subset of the plurality of ports, and wherein each of the plurality of forwarding pipelines contains a respective forwarding table corresponding to the respective subset of the plurality of ports managed by the forwarding pipeline; and
logic circuit configured to:
receive a plurality of data packets on ports in the plurality of ports;
based on the received plurality of data packets, determine a plurality of update operations to be performed on the forwarding tables; and
perform the plurality of update operations on the forwarding tables for each of the plurality of forwarding pipelines, such that all the forwarding tables across all forwarding pipelines the plurality of forwarding pipelines are synchronized, thereby enabling updated information relating to the received plurality of data packets to be used by all forwarding pipelines of the plurality of forwarding pipelines, wherein the logic circuit is further configured to:
determine that a first update operation and a second update operation of the plurality of update operations refer to a same memory bank of the forwarding tables, such that the first update operation and the second update operation are performed in serial and are not performed together in a single clock cycle;
select the first update operation to be performed on a current clock cycle;
perform the selected update operation on the current clock cycle; and
write the second update operation to a write cache for execution on a subsequent clock cycle.

14. The network switch of claim 13 , wherein the forwarding table on each of the plurality of forwarding pipelines contains a global data set corresponding to all of the plurality of forwarding pipelines.

15. The network switch of claim 14 , wherein the forwarding tables on each of the plurality of forwarding pipelines are identical, wherein the forwarding tables provide a single logical routing

Assignees

• Cisco Tech Inc

Inventors

• Wu Wanli
• Bhattacharya Saikat

Classifications

• G06F15/167 Primary

  using a common memory, e.g. mailbox · CPC title

• H04L49/3009 Primary

  Header conversion, routing tables or routing tags · CPC title