Data transfer manager

Patent metadata

Field	Value
Publication number	US-9658975-B2
Application number	US-201213563683-A
Country	US
Kind code	B2
Filing date	Jul 31, 2012
Priority date	Jul 31, 2012
Publication date	May 23, 2017
Grant date	May 23, 2017

Abstract

Techniques are disclosed relating to a system that implements direct memory access (DMA). In one embodiment, an apparatus is disclosed that includes a dedicated data transfer management (DTM) circuit. The DTM circuit is configured to provide commands to a direct memory access (DMA) controller coupled to a bus to facilitate the DMA controller retrieving portions of a data object to be transmitted to a peripheral circuit via the bus. In some embodiments, the DTM is configured to assemble a data packet having a payload supplied by a processor, where the DTM circuit is configured to assemble the data packet by generating direct memory access (DMA) requests for the DMA controller. In such an embodiment, the DMA requests cause a plurality of peripheral circuits coupled to the bus to transfer portions of the data packet over the bus.

First claim

What is claimed is:

1. An apparatus, comprising:
a direct memory access (DMA) controller coupled to a bus;
a data transfer management (DTM) circuit;
a processor configured to execute program instructions to configure the DTM circuit to provide DMA requests to the DMA controller, wherein the DMA requests cause the DMA controller to perform:
retrieving a data object; and
transmitting the data object to a peripheral circuit via the bus.

2. The apparatus of claim 1 , wherein the data object is a data packet, and wherein the DTM circuit is configured to provide requests to the DMA controller in a manner that causes an assembly of the data packet.

3. The apparatus of claim 2 , wherein the peripheral circuit is coupled to a radio circuit configured to transmit the data packet via an antenna.

4. The apparatus of claim 1 , wherein the DTM circuit is configured to receive DMA requests from a plurality of peripheral circuits coupled to the bus, wherein the plurality of peripheral circuits are configured to generate portions of the data object, and wherein the DTM circuit is configured to provide the requests to the DMA controller based on the received DMA requests.

5. The apparatus of claim 4 , wherein the DTM circuit is configured to provide a request to the DMA controller in response to receiving DMA requests from two of the plurality of peripheral circuits, wherein the DTM circuit is configured to receive, from the DMA controller, an acknowledgement corresponding to the request, and wherein the DTM circuit is configured to provide the acknowledgement to the two peripheral circuits.

6. The apparatus of claim 1 , wherein the DTM circuit is configured to implement a state machine, and wherein the DTM circuit is configured to generate the requests provided to the DMA controller according to the state machine.

7. The apparatus of claim 1 , wherein the DTM circuit is configured to receive configuration information generated by the processor, and wherein the processor is configured to enter a reduced power mode while the DTM circuit provides the requests to the DMA controller.

8. An apparatus, comprising:
a data transfer management (DTM) circuit configurable by a processor to coordinate assembly of a data packet, wherein the DTM circuit is configured to coordinate assembly by generating direct memory access (DMA) requests for a DMA controller, wherein the DMA requests cause a plurality of peripheral circuits coupled to a bus to transfer portions of the data packet over the bus.

9. The apparatus of claim 8 , wherein the DTM circuit is configured to initiate, via the DMA controller, a peripheral-to-peripheral exchange that transfers data from a first of the plurality of peripheral circuits to a second of the plurality of peripheral circuits.

10. The apparatus of claim 8 , wherein the DTM circuit is configured to generate DMA requests directed to a plurality of DMA channels of the DMA controller.

11. The apparatus of claim 8 , wherein a first of the plurality of peripheral circuits is configured to encrypt at least a portion of the data packet, and wherein a second of the plurality of peripheral circuits is configured to generate a checksum value.

12. The apparatus of claim 8 , wherein the DTM circuit is further configured to coordinate disassembly of a received data packet, by generating DMA requests for the DMA controller, and wherein the apparatus is configured to receive the data packet via a radio circuit.

13. The apparatus of claim 8 , wherein the DTM circuit is configured to generate DMA requests according to a state machine implemented by the DTM circuit, wherein the state machine is configured to identify a source and a destination for one or more DMA transfers via the bus.

14. The apparatus of claim 13 , wherein the DTM circuit is coupled to the bus, and wherein the DTM circuit is configured to operate as a bus master of the bus to retrieve state information of the state machine from memory.

15. A method, comprising:
a data transfer management (DTM) circuit receiving configuration information from a processor, wherein the configuration information is usable to assemble a data packet;
the DTM circuit receiving a first set of DMA requests from a plurality of peripheral circuits configured to generate portions of the data packet; and
the DTM circuit issuing a second set of DMA requests to a DMA controller, wherein the DMA controller causes the generated portions to be presented to a circuit, and wherein the second set of DMA requests are issued based on the first set of DMA requests and the configuration information.

16. The method of claim 15 , wherein the second set of DMA requests are issued according to a state machine that transitions from one state to another state based on a value of a counter, and wherein the method further comprises:
the DTM circuit adjusting the value of the counter in response to issuing a DMA request of the second set of DMA requests.

17. The method of claim 15 , wherein the issuing includes issuing a given DMA request to the DMA controller in response to receiving DMA requests from two of the plurality of peripheral circuits, and wherein the method further comprises:
the DTM circuit routing, to the two peripheral circuits, an acknowledgment signal received from the DMA controller responsive to the given DMA request, wherein the two peripheral circuits are configured to coordinate a transmission of data between the two peripheral circuits based on the routed acknowledgement signal.

18. The method of claim 15 , wherein the second set of DMA requests includes requests issued to different DMA channels of the DMA controller, and wherein the DMA controller causes the generated portions to be presented to a radio circuit.

19. The method of claim 15 , further comprising:
the DTM circuit receiving a third set of DMA requests from ones of the plurality of peripheral circuits configured to operate on portions of a received data packet; and
the DTM circuit issuing a fourth set of DMA requests to the DMA controller, wherein the DMA controller causes the portions to be presented to ones of the plurality of peripheral circuits to facilitate disassembly of the received data packet, and wherein the fourth set of DMA requests are issued based on the third set of DMA requests.

20. The method of claim 19 , wherein the fourth set of DMA requests are issued according to a state machine that coordinates disassembly of the received data packet and transitions from one state to another state based on a value of a counter, and wherein the method further comprises:
the DTM circuit adjusting the value of the counter in response to issuing a DMA request of the fourth set of DMA requests.

Assignees

• Fernald Kenneth W
• Silicon Lab Inc

Inventors

• Fernald Kenneth W

Classifications

• G06F13/28 Primary

  using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) · CPC title

• Y02B60/1228

  Cross-Sectional Technologies · mapped topic

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title