Using a printed circuit to offset charge during capacitive sensing

Patent metadata

Field	Value
Publication number	US-9658722-B2
Application number	US-201314038466-A
Country	US
Kind code	B2
Filing date	Sep 26, 2013
Priority date	Sep 26, 2013
Publication date	May 23, 2017
Grant date	May 23, 2017

Abstract

In a method of capacitive sensing an absolute capacitive sensing signal is driven through at least one of a plurality of routing traces of a printed circuit. Absolute capacitive sensing is performed with at least one sensor electrode of a plurality of sensor electrodes in a sensor electrode pattern. The at least one sensor electrode is coupled with the at least one of the plurality of routing traces. An offsetting signal is transmitted on a parallel conductor overlapping the at least one of the plurality of routing traces, such that charge is offset from the at least one of the plurality of routing traces during the absolute capacitive sensing.

First claim

What is claimed is:

1. A method of capacitive sensing, said method comprising:
driving an absolute capacitive sensing signal through at least one of a plurality of routing traces of a printed circuit;
performing absolute capacitive sensing with at least one sensor electrode of a plurality of sensor electrodes in a sensor electrode pattern, wherein said at least one sensor electrode of said plurality of said sensor electrodes is coupled with said at least one of said plurality of said routing traces; and
transmitting an offsetting signal on a first parallel conductor, wherein said first parallel conductor overlaps said at least one of said plurality of said routing traces longitudinally over a span where said first parallel conductor and said plurality of said routing traces run in parallel with one another but does not overlap any of said plurality of said sensor electrodes, such that charge is offset from said at least one of said plurality of said routing traces during said absolute capacitive sensing; and
transmitting a guarding signal on a second parallel conductor, wherein said second parallel conductor overlaps at least one of said plurality of said routing traces longitudinally over a span where said second parallel conductor and said at least one of said plurality of said routing traces run in parallel with one another but does not overlap any of said plurality of said sensor electrodes, such that a portion of said at least one of said plurality of said routing traces that is overlapped by said second parallel conductor is guarded during said absolute capacitive sensing, and
wherein said first parallel conductor and said second parallel conductor overlap different portions of the same said at least one of said plurality of said routing traces.

2. The method as recited in claim 1 , wherein said transmitting said offsetting signal on said first parallel conductor such that charge is offset from said at least one of said plurality of said routing traces during said absolute capacitive sensing comprises:
transmitting said offsetting signal as an in-phase signal to said absolute capacitive sensing signal.

3. The method as recited in claim 2 , wherein said transmitting said offsetting signal as said in-phase signal to said absolute capacitive sensing signal comprises:
setting the amplitude of said offsetting signal at a level greater than the amplitude of said absolute capacitive sensing signal.

4. The method as recited in claim 1 , further comprising:
performing transcapacitive sensing using said plurality of said sensor electrodes at a separate time from said absolute capacitive sensing; and
coupling said first parallel conductor with ground during said transcapacitive sensing.

5. A processing system comprising:
a sensor module configured to:
drive an absolute capacitive sensing signal through at least one of a plurality of routing traces on a printed circuit to perform absolute capacitive sensing with at least one sensor electrode of a plurality of sensor electrodes in a sensor electrode pattern, wherein said at least one sensor electrode is coupled with said at least one of said plurality of routing traces; and
transmit an offsetting signal on a first parallel conductor, wherein said first parallel conductor overlaps said at least one of said plurality of routing traces longitudinally over a span where said first parallel conductor and said plurality of said routing traces run in parallel with one another but does not overlap any of said sensor electrodes, such that charge is offset from said at least one of said plurality of said routing traces during said absolute capacitive sensing;
transmit a guarding signal on a second parallel conductor, wherein said second parallel conductor overlaps said at least one of plurality of routing traces longitudinally over a span where the second parallel conductor and said plurality of said routing traces run in parallel with one another but does not overlap any of said sensor electrodes, such that a portion of said at least one of said plurality of said routing traces that is overlapped by said second parallel conductor is guarded during said absolute capacitive sensing, and wherein said first parallel conductor and said second parallel conductor overlap different portions of the same said at least one of said plurality of said routing traces; and

a determination module configured to determine input within a sensing region of said plurality of said sensor electrodes based on said absolute capacitive sensing.

6. The processing system of claim 5 , wherein said sensor module is further configured to:
perform transcapacitive sensing using said sensor electrodes at a separate time from said absolute capacitive sensing; and
couple said first parallel conductor with ground during said transcapacitive sensing; and
wherein said determination module is further configured to determine input within a sensing region of said plurality of said sensor electrodes based on said transcapacitive sensing.

7. The processing system of claim 5 , wherein said sensor module is configured to transmit said offsetting signal as an in-phase signal to said absolute capacitive sensing signal.

8. The processing system of claim 7 , wherein said sensor module is configured to set the amplitude of said offsetting signal at a level greater than the amplitude of said absolute capacitive sensing signal such that charge is offset from said plurality of said routing traces.

9. A capacitive sensing input device, said capacitive sensing input device comprising:
a sensor electrode pattern comprising a plurality of sensor electrodes;
a processing system configured to operate said plurality of sensor electrodes to perform absolute capacitive sensing; and
a printed circuit comprising:
a first plurality of routing traces and a second plurality of routing traces configured to communicatively couple signals between said plurality of sensor electrodes and said processing system;
a first parallel conductor, wherein said first parallel conductor overlaps said first plurality of said routing traces longitudinally over a span where said first parallel conductor and said first plurality of said routing traces run in parallel with one another but does not overlap any of said plurality of sensor electrodes, said first parallel conductor coupled with said processing system and configured to offset charge from said first plurality of said routing traces during said absolute capacitive sensing; and
a second parallel conductor, wherein said parallel conductor overlaps said second plurality of said routing traces longitudinally over a span where said second parallel conductor and said second plurality of said routing traces run in parallel with one another but does not overlap any of said plurality of sensor electrodes, said second parallel conductor coupled with said processing system and configured to guard said second plurality of said routing traces with an in-phase signal of substantially the same amplitude as signals transmitted on said plurality of said routing traces during said absolute capacitive sensing, and
wherein said first parallel conductor overlaps said first plurality of said routing traces at different locations than said second parallel conductor overlaps said second plurality of said routing traces.

10. The input device of claim 9 , wherein said first plurality of said routing traces and said second plurality of said routing traces share no routing traces in common.

11. The input device of claim 9 , wherein said processing system is further configured to:
couple said first parallel conductor with an in-phase signal to signals transmitted on said first plurality of said rou

Assignees

• Synaptics Inc

Inventors

• Schwartz Adam

Classifications

• G06F2203/04107

  Shielding in digitiser, i.e. guard or shielding arrangements, mostly for capacitive touchscreens, e.g. driven shields, driven grounds · CPC title

• G06F3/0418 Primary

  for error correction or compensation, e.g. based on parallax, calibration or alignment · CPC title

• G06F3/044 Primary

  by capacitive means · CPC title

• G06F3/0446 Primary

  using a grid-like structure of electrodes in at least two directions, e.g. using row and column electrodes · CPC title

• G06F3/04164

  Connections between sensors and controllers, e.g. routing lines between electrodes and connection pads · CPC title