Thermally-aware throttling in a three-dimensional processor stack

Patent metadata

Field	Value
Publication number	US-9658663-B2
Application number	US-201514862044-A
Country	US
Kind code	B2
Filing date	Sep 22, 2015
Priority date	Sep 22, 2015
Publication date	May 23, 2017
Grant date	May 23, 2017

Abstract

A three-dimensional (3-D) processor stack includes a plurality of processor cores implemented in a plurality of layers. A controller is to selectively throttle one or more of a plurality of processor cores in response to detecting a thermal event. The controller selectively throttles the one or more of the plurality of processor cores based on values of thermal couplings between the plurality of layers and based on measures of criticality of threads executing on the plurality of processor cores.

First claim

What is claimed is:

1. A method comprising:
generating values of thermal couplings between a plurality of layers of a three-dimensional processor stack that includes a plurality of processor cores, wherein at least one of the plurality of processor cores is implemented in each of the plurality of layers, and wherein the values of the thermal couplings indicate temperature changes in each of the plurality of layers as a function of temperature changes in each of the other layers; and
in response to a thermal event in one of the plurality of layers, selectively throttling at least one of the plurality of processor cores implemented in the plurality of layers based on the values of the thermal couplings and measures of criticality of threads executing on the plurality of processor cores.

2. The method of claim 1 , wherein selectively throttling the at least one of the plurality of processor cores comprises selectively throttling the at least one of the plurality of processor cores based on latencies between temperature changes in the plurality of layers.

3. The method of claim 1 , further comprising:
detecting the thermal event at a first processor core implemented in a first layer; and
determining whether a first thread executing on the first processor core is a critical thread based on a measure of criticality of the first thread.

4. The method of claim 3 , wherein determining whether the first thread is a critical thread comprises determining whether the first thread is a critical thread based on at least one of a criticality indicator provided by an operating system and a value of a hardware event counter associated with the first thread.

5. The method of claim 1 , wherein generating the values of the thermal couplings further comprises:
iteratively executing a predetermined code on the plurality of processor cores in each of the plurality of layers; and
measuring temperatures in each of the plurality of layers in response to executing the predetermined code on the plurality of processor cores in each of the plurality of layers; and
determining the values of the thermal couplings between the plurality of layers based on the measured temperatures.

6. The method of claim 5 , wherein determining the values of the thermal couplings comprises determining values of latencies between temperature changes in each of the plurality of processor cores in each of the plurality of layers.

7. A method comprising:
generating values of thermal couplings between a plurality of layers of a three-dimensional processor stack;
detecting a thermal event at a first processor core implemented in a first layer; and
determining whether a first thread executing on the first processor core is a critical thread based on a measure of criticality of the first thread; and
in response to the thermal event in one of the plurality of layers, selectively throttling at least one of a plurality of processor cores implemented in the plurality of layers based on the values of the thermal couplings and measures of criticality of threads executing on the plurality of processor cores, wherein selectively throttling the at least one of the plurality of processor cores comprises selectively throttling at least one second processor core implemented in a second layer in response to the first thread being a critical thread and a second thread executing on the second processor core not being a critical thread.

8. The method of claim 7 , wherein selectively throttling the at least one second processor core comprises selectively throttling the at least one second processor core based on a thermal coupling between the first layer and the second layer.

9. The method of claim 7 , further comprising:
determining whether the thermal event is resolved by throttling the at least one second processor core; and
throttling at least one other processor core in response to determining that the thermal event has not been resolved.

10. An apparatus comprising:
a three-dimensional processor stack comprising a plurality of processor cores implemented in a plurality of layers, wherein at least one of the plurality of processor cores is implemented in each of the plurality of layers; and
a controller to:
generate values of thermal couplings between the plurality of layers based on temperatures measured in the plurality of layers, wherein the values of the thermal couplings indicate temperature changes in each of the plurality of layers as a function of temperature changes in each of the other layers; and
selectively throttle at least one of the plurality of processor cores in response to detecting a thermal event, wherein the controller is to selectively throttle the at least one of a plurality of processor cores based on values of thermal couplings between the plurality of layers and based on measures of criticality of threads executing on the plurality of processor cores.

11. The apparatus of claim 10 , wherein the controller is to selectively throttle the at least one of the plurality of processor cores based on latencies between temperature changes in the plurality of layers.

12. The apparatus of claim 10 , wherein the controller is to detect the thermal event at a first processor core implemented in a first layer and determine whether a first thread executing on the first processor core is a critical thread based on a measure of criticality of the first thread.

13. The apparatus of claim 12 , wherein the controller is to determine whether the first thread is a critical thread based on at least one of a criticality indicator provided by an operating system and a value of a hardware event counter associated with the first thread.

14. The apparatus of claim 10 , wherein the plurality of processor cores in each of the plurality of layers are to iteratively execute a predetermined code, and wherein the apparatus further comprises:
a plurality of sensors to measure temperatures in each of the plurality of layers in response to executing the predetermined code on the plurality of processor cores in each of the plurality of layers, and wherein the controller is to generate the values of the thermal couplings between the plurality of layers based on the measured temperatures.

15. The apparatus of claim 14 , wherein the controller is to determine values of latencies between temperature changes in each of the plurality of processor cores in each of the plurality of layers.

16. An apparatus comprising:
a three-dimensional processor stack comprising a plurality of processor cores implemented in a plurality of layers; and
a controller to:
generate values of thermal couplings between the plurality of layers based on temperatures measured in the plurality of layers;
detect a thermal event at a first processor core implemented in a first layer;
determine whether a first thread executing on the first processor core is a critical thread based on a measure of criticality of the first thread; and

selectively throttle at least one of the plurality of processor cores in response to detecting the thermal event, wherein the controller is to selectively throttle the at least one of a plurality of processor cores based on values of thermal couplings between the plurality of layers and based on measures of criticality of threads executing on the plurality of processor cores, wherein the controller is to selectively throttle at least one second processor core implemented in a second layer in response to the first thread being a critical thread and a second thread executing on the second processor core not being a critical thread.

17. The appar

Assignees

• Advanced Micro Devices Inc

Inventors

• Huang Wei
• Arora Manish
• Eckert Yasuko
• Paul Indrani

Classifications

• G06F11/3058

  Monitoring arrangements for monitoring environmental properties or parameters of the computing system or of the computing system component, e.g. monitoring of power, currents, temperature, humidity, position, vibrations (thermal management in cooling arrangements of a computing system G06F1/206) · CPC title

• G06F1/3206

  Monitoring of events, devices or parameters that trigger a change in power modality · CPC title

• G06T1/20

  Processor architectures; Processor configuration, e.g. pipelining · CPC title

• G06F1/206 Primary

  comprising thermal management · CPC title

• G06F1/3296

  by lowering the supply or operating voltage · CPC title