Apparatus and methods for scalable photonic packet architectures using PIC switches

Patent metadata

Field	Value
Publication number	US-9658403-B2
Application number	US-201514695970-A
Country	US
Kind code	B2
Filing date	Apr 24, 2015
Priority date	Apr 25, 2014
Publication date	May 23, 2017
Grant date	May 23, 2017

Abstract

Embodiments are provided for scalable photonic packet fabric architectures using photonic integrated circuit switches. The architectures use compact size silicon photonic circuits that can be arranged in a combined centralized and distributed manner. In an embodiment, an optical switch structure comprises a plurality of core photonic based switches and a plurality of photonic interface units (PIUs) optically coupled to the core photonic based switches and to a plurality of groups of top-of-rack switches (TORs). Each PIU comprises a N×N silicon photonic (SiP) switch optically coupled to a group of TORs associated with the PIU from the groups of TORs, where N is a number of the TORs in each group. The PIU also comprises a plurality of 1×P SiP switches coupled to the group of TORs associated with the PIU and to the core photonic based switches, where P is a number of the core photonic based switches.

First claim

What is claimed is:

1. An optical switch for switching optical packets comprising:
a first photonic interface unit (PIU) comprising:
a N×N silicon photonic (SiP) switch connecting N top of rack switches (TORs) to each other, wherein each TOR has M interfaces, and wherein N and M are integers; and
a plurality of 1×P SiP switches, wherein each of the 1×P SiP switches connects a respective interface of the M interfaces of a respective TOR to P core photonic-based switches, and wherein P is an integer.

2. The optical switch of claim 1 , wherein the core photonic-based switches comprise N×N SiP switches.

3. The optical switch of claim 1 , wherein each core photonic-based switch is connected to G PIUs including the first PIU, where G is an integer.

4. The optical switch of claim 3 , wherein the N×N SiP switch and each of the 1×P SiP switches is integrated on a respective chip.

5. The optical switch of claim 3 , wherein the plurality of 1×P SiP switches are optically coupled to the P core photonic-based switches through optical fibers.

6. The optical switch of claim 3 , wherein the P core photonic-based switches comprise G N ×G N SiP switches, wherein each G N ×G N switch is a G×G SIP switch with G inputs and G outputs.

7. The optical switch of claim 1 , wherein the core photonic-based switches comprise ring based optical switches.

8. The optical switch of claim 7 , wherein the ring based optical switches comprise a plurality of pairs of clockwise ring based optical switches and corresponding counter-clockwise ring based optical switches.

9. The optical switch of claim 7 , wherein each of the ring based optical switches is connected to G similar optical switches including the optical switch through G nodes and allows an optical packet a maximum traversal distance of G/2-1, where G is an integer.

10. The optical switch of claim 7 , wherein a total quantity of the ring based optical switches is determined to increase spatial reuse or allow optical packets a maximum traversal distance of about 1 inside the ring based optical switches.

11. The optical switch of claim 7 , wherein each ring based optical switch of the ring based optical switches comprises:
a plurality of nodes for connecting to a plurality of optical switches including the optical switch, wherein each node comprises a pair of 1×N and N×1 SiP switches coupled to a corresponding optical switch of the optical switches, and a 2×2 SiP switch coupled to the pair of 1×N and N×1 SiP switches; and
a pair of optical paths arranged in a ring across the nodes and coupled to the pair of 1×N and N×1 SiP switches through the 2×2 SiP switch.

12. The optical switch of claim 11 , wherein the pair of optical paths is one of a pair of optical fibers and a pair of optical waveguides.

13. The optical switch of claim 11 , wherein each of the 1×N switches and each of the N×1 SiP switches is a cascade of log N levels of 1×2 SiP switches, and wherein the 2×2 SiP switch is a pair of 1×2 and 2×1 SiP switches.

14. A method of operating an optical switch structure with photonic integrated circuit (PIC) switches, the method comprising:
receiving, at photonic interface unit (PIU) from a top-of-rack switch (TOR), an optical packet;
determining whether the optical packet has a destination TOR directly coupled to the PIU; and
performing one of:
sending, through a N×N silicon photonic (SiP) switch of the PIU, the optical packet to the destination TOR upon determining the destination TOR is directly coupled to the PIU, or
sending, through a 1×P SiP switch of the PIU, the optical packet to a core photonic-based switch coupled to the destination TOR upon determining the destination TOR is not directly coupled to the PIU, wherein N and P are integers.

15. The method of claim 14 further comprising, after sending the optical packet to the core photonic-based switch:
sending the optical packet from the core photonic-based switch to a second optical switch coupled to the destination TOR; and
sending, through a 1×P SiP switch of the second optical switch, the optical packet to the destination TOR.

16. The method of claim 15 , wherein sending the optical packet to the core photonic-based switch and sending the optical packet from the core photonic-based switch to the second optical switch comprises sending the optical packet through a ring switch fabric in the core photonic-based switch.

17. The method of claim 15 , wherein sending the optical packet to the core photonic-based switch and sending the optical packet from the core photonic-based switch to the second optical switch comprises sending the optical packet through a SiP switch fabric in the core photonic-based switch.

Assignees

• Huawei Tech Co Ltd

Inventors

• Mehrvar Hamid
• Ma Huixiao
• Bernier Eric

Classifications

• H04Q2011/0054

  Distribute-route · CPC title

• H04Q2011/005

  Arbitration and scheduling · CPC title

• H04Q2011/0045

  Synchronisation · CPC title

• H04Q2011/0039

  Electrical control · CPC title

• H04Q2011/0024

  using space switching · CPC title