Topology of distributing and connecting LEDs in a large area matrix

US9655183B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9655183-B2
Application numberUS-201214241111-A
CountryUS
Kind codeB2
Filing dateAug 31, 2012
Priority dateSep 6, 2011
Publication dateMay 16, 2017
Grant dateMay 16, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A LED circuit comprises an array of LEDs is arranged in a matrix. The matrix is connected to at least three power rail lines. The LEDs are formed as a first LED arrangement ( 34 ) between a first power rail line ( 30 ) and a second power rail line ( 32 ) and a second LED arrangement ( 36 ) between the second power rail line ( 32 ) and a third power rail line ( 30 ) of the same voltage as the first power rail line. This means there are alternating power rail lines interspersed with the matrix of LEDs. This enables the driving voltages to be kept low and it improves scalability of the design.

First claim

Opening claim text (preview).

The invention claimed is: 1. An LED circuit, comprising: an array of LEDs arranged in a first matrix, each LED connected within the first matrix by connecting wires; the first matrix interposed between a pair of voltage rails; the pair of voltage rails are connected to at least three power rail lines distributed across the area of the first matrix; wherein the LEDs connected within the first matrix include a first LED arrangement between a first power rail line and a second, adjacent power rail line; a second LED arrangement between the second power rail line and a third power rail line configured be of the same electrical potential as the power rail line; the third power rail line adjacent the second power rail line and on the opposite side of the second power rail line compared to the first power rail line; the first and second LED arrangements comprising a plurality of parallel pairs of LEDs in series alignment, each of said plurality of parallel pairs of LEDs being at least two LEDs in parallel and including a bridge interposed between each of said plurality of parallel pairs of LEDs, wherein the first and second arrangements are aligned cathode-to-cathode; an array of LEDs arranged in a second matrix; the second matrix interposed between the pair of voltage rails, wherein the second matrix is connected in parallel alignment with the first matrix and includes a third LED arrangement connected to the third power rail line; and the third LED arrangement comprising a plurality of parallel pairs of LEDs in series alignment, each of said plurality of parallel pairs of LEDs being at least two LEDs in parallel and including a bridge interposed between each of said plurality of parallel pairs of LEDs, wherein the second LED arrangement of the first matrix and the third LED arrangement of the second matrix are aligned anode-to-anode.

Assignees

Inventors

Classifications

  • G09G3/32Primary

    semiconductive, e.g. using light-emitting diodes [LED] · CPC title

  • with an active control inside an LED matrix · CPC title

  • Layout of electrodes and connections · CPC title

  • with LEDs · CPC title

  • Light sources using semiconductor devices as light-generating elements, e.g. using light-emitting diodes [LED] or lasers · CPC title

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Frequently asked questions

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What does patent US9655183B2 cover?
A LED circuit comprises an array of LEDs is arranged in a matrix. The matrix is connected to at least three power rail lines. The LEDs are formed as a first LED arrangement ( 34 ) between a first power rail line ( 30 ) and a second power rail line ( 32 ) and a second LED arrangement ( 36 ) between the second power rail line ( 32 ) and a third power rail line ( 30 ) of the same voltage as the fi…
Who is the assignee on this patent?
Krijn Marcellinus Petrus Carolus Michael, Weekamp Johannes Wilhelmus, Cornelissen Hugo Johan, and 1 more
What technology area does this patent fall under?
Primary CPC classification G09G3/32. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue May 16 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).