Pixels with a global shutter and high dynamic range

Patent metadata

Field	Value
Publication number	US-9654712-B2
Application number	US-201514877722-A
Country	US
Kind code	B2
Filing date	Oct 7, 2015
Priority date	Oct 7, 2015
Publication date	May 16, 2017
Grant date	May 16, 2017

Abstract

An imaging pixel may be provided with a photodiode and a floating diffusion region. The pixel may include at least one storage capacitor that can store charge from the floating diffusion region. The at least one storage capacitor may provide global shutter functionality for the pixel. Multiple storage capacitors may be provided for correlated double sampling (CDS) techniques and high dynamic range (HDR) images. The imaging pixel may have an upper substrate layer and a lower substrate layer. The photodiode may be formed in the upper substrate layer, and the storage capacitors may be formed in the lower substrate layer. A interconnect layer may couple pixel circuitry in the upper substrate layer to pixel circuitry in the lower substrate layer.

First claim

What is claimed is:

1. An imaging pixel comprising:
an upper substrate layer;
a lower substrate layer;
a floating diffusion region;
a photodiode in the upper substrate layer that is coupled to the floating diffusion region;
an interconnect layer interposed between the upper substrate layer and the lower substrate layer that couples the upper substrate layer to the lower substrate layer;
a first storage capacitor in the lower substrate layer;
a source follower transistor coupled to the floating diffusion region;
an additional floating diffusion region;
an additional source follower transistor coupled to the additional floating diffusion region; and
a sampling transistor coupled between the source follower transistor and the additional floating diffusion region, wherein the floating diffusion region and the source follower transistor are formed in the upper substrate layer, and wherein the additional floating diffusion region and the additional source follower transistor are formed in the lower substrate layer.

2. The imaging pixel defined in claim 1 , wherein the interconnect layer is interposed between the source follower transistor and the sampling transistor.

3. The imaging pixel defined in claim 2 , wherein the sampling transistor is formed in the lower substrate layer.

4. The imaging pixel defined in claim 3 , further comprising:
second and third storage capacitors formed in the lower substrate layer.

5. An imaging pixel comprising:
an upper substrate layer;
a lower substrate layer;
a floating diffusion region;
a photodiode in the upper substrate layer that is coupled to the floating diffusion region;
an interconnect layer interposed between the upper substrate layer and the lower substrate layer that couples the upper substrate layer to the lower substrate layer;
a first storage capacitor in the lower substrate layer; and
a transfer transistor formed in the upper substrate layer that is coupled to the floating diffusion region, wherein the floating diffusion region is formed in the lower substrate layer, and wherein the interconnect layer is interposed between the transfer transistor and the floating diffusion region.

6. The imaging pixel defined in claim 5 , further comprising:
second and third storage capacitors formed in the lower substrate layer.

7. An imaging pixel comprising:
a first floating diffusion region;
a photodiode coupled to the first floating diffusion region;
a first source follower transistor coupled to the first floating diffusion region;
a second floating diffusion region;
a second source follower transistor coupled to the second floating diffusion region;
a first storage capacitor;
a second storage capacitor;
a third storage capacitor;
a sampling transistor interposed between the second floating diffusion region and the first source follower transistor;
a transistor interposed between the sampling transistor and the first storage capacitor;
a transistor interposed between the sampling transistor and the second storage capacitor; and
a transistor interposed between the sampling transistor and the third storage capacitor.

8. The imaging pixel defined in claim 7 , further comprising:
a first reset transistor interposed between the first floating diffusion region and a first positive power supply terminal; and
a second reset transistor interposed between the second floating diffusion region and a second positive power supply terminal.

9. The imaging pixel defined in claim 8 , further comprising a row select transistor interposed between an output line and the second source follower transistor.

10. A method of operating an imaging pixel, wherein the imaging pixel comprises a photodiode, a floating diffusion region, a first storage capacitor, a second storage capacitor, and a third storage capacitor, the method comprising:
with the photodiode, accumulating a first amount of charge for a first time period;
resetting the floating diffusion region to a power supply voltage;
after resetting the floating diffusion region to the power supply voltage, sampling a second amount of charge at the floating diffusion region and storing the second amount of charge in the first storage capacitor;
transferring the first amount of charge to the floating diffusion region;
after transferring the first amount of charge to the floating diffusion region, sampling the first amount of charge at the floating diffusion region and storing the first amount of charge in the second storage capacitor;
with the photodiode, accumulating a third amount of charge for a second time period;
transferring the third amount of charge to the floating diffusion region; and
after transferring the third amount of charge to the floating diffusion region, sampling the third amount of charge at the floating diffusion region and storing the third amount of charge in the third storage capacitor.

11. The method defined in claim 10 , wherein the imaging pixel further comprises a fourth storage capacitor, the method further comprising:
with the photodiode, accumulating a fourth amount of charge for a third time period;
transferring the fourth amount of charge to the floating diffusion region; and
after transferring the fourth amount of charge to the floating diffusion region, sampling the fourth amount of charge at the floating diffusion region and storing the fourth amount of charge in the fourth storage capacitor.

12. The method defined in claim 10 , wherein the imaging pixel further comprises a fourth storage capacitor, the method further comprising:
before transferring the third amount of charge to the floating diffusion region and after sampling the second amount of charge at the floating diffusion region, resetting the floating diffusion region to the power supply voltage; and
after resetting the floating diffusion region to the power supply voltage and before transferring the third amount of charge to the floating diffusion region, sampling a fourth amount of charge at the floating diffusion region and storing the fourth amount of charge in the fourth storage capacitor.

13. The method defined in claim 10 , wherein the first time period is longer than the second time period.

14. The method defined in claim 10 , wherein the imaging pixel further comprises a first source follower transistor coupled to the floating diffusion region, an additional floating diffusion region, and a second source follower transistor coupled to the additional floating diffusion region.

15. The method defined in claim 14 , wherein the imaging pixel further comprises a transistor interposed between the first source follower transistor and the additional floating diffusion region, and wherein sampling the first amount of charge at the floating diffusion region and storing the first amount of charge in the second storage capacitor comprises turning on the transistor.

Assignees

• Semiconductor Components Ind Llc

Inventors

• Hong Sungkwon C

Classifications

• H04N23/12

  with one sensor only · CPC title

• H04N25/76 Primary

  Addressed sensors, e.g. MOS or CMOS sensors · CPC title

• H04N25/771

  comprising storage means other than floating diffusion · CPC title

• H04N25/79

  Arrangements of circuitry being divided between different or multiple substrates, chips or circuit boards, e.g. stacked image sensors · CPC title

• H04N25/589

  with different integration times, e.g. short and long exposures · CPC title