Thin film transistor, its manufacturing method and display device

Patent metadata

Field	Value
Publication number	US-9653578-B2
Application number	US-201514744838-A
Country	US
Kind code	B2
Filing date	Jun 19, 2015
Priority date	Mar 26, 2015
Publication date	May 16, 2017
Grant date	May 16, 2017

Abstract

The present disclosure relates to the field of display technology, and provides a TFT, its manufacturing method and a display device. A first region of an active layer of the TFT corresponding to a gap between a source electrode and a drain electrode includes a metallic oxide semiconductor layer and a silicon semiconductor layer arranged on the metallic oxide semiconductor layer. The source electrode and the drain electrode are directly lapped onto the active layer.

First claim

What is claimed is:

1. A thin film transistor (TFT): comprising an active layer, and a source electrode and a drain electrode lapped onto the active layer, the active layer comprising a source region in contact with the source electrode, a drain region in contact with the drain electrode, and a first region corresponding to a gap between the source electrode and the drain electrode, wherein the first region of the active layer comprises a metallic oxide semiconductor layer and a silicon semiconductor layer arranged on the metallic oxide semiconductor layer, the silicon semiconductor layer consists of an amorphous Silicon (a-Si) layer, and the metallic oxide semiconductor layer is arranged on a gate insulating layer and is in direct contact with the gate insulating layer.

2. The TFT according to claim 1 , wherein the source region and the drain region of the active layer consist of the metallic oxide semiconductor layer and the a-Si layer arranged on the metallic oxide semiconductor layer.

3. The TFT according to claim 1 , wherein the source region and the drain region of the active layer consist of the metallic oxide semiconductor layer as well as the a-Si layer and a heavily-doped a-Si layer sequentially arranged on the metallic oxide semiconductor layer.

4. The TFT according to claim 1 , wherein the silicon semiconductor layer consists of a heavily-doped a-Si layer, and the source region and the drain region of the active layer consist of the metallic oxide semiconductor layer and the heavily-doped a-Si layer arranged on the metallic oxide semiconductor layer.

5. The TFT according to claim 1 , wherein the source region and the drain region of the active layer consist of the metallic oxide semiconductor layer.

6. A method for manufacturing a thin film transistor (TFT), wherein the TFT comprises: an active layer, and a source electrode and a drain electrode lapped onto the active layer, the active layer comprising a source region in contact with the source electrode, a drain region in contact with the drain electrode, and a first region corresponding to a gap between the source electrode and the drain electrode, wherein the first region of the active layer comprises a metallic oxide semiconductor layer and a silicon semiconductor layer arranged on the metallic oxide semiconductor layer, the silicon semiconductor layer consists of an amorphous Silicon (a-Si) layer, and the metallic oxide semiconductor layer is arranged on a gate insulating layer and is in direct contact with the gate insulating layer;
wherein the method comprises: a step of forming the active layer and a step of forming the source electrode and the drain electrode, wherein the step of forming the first region of the active layer comprises:
forming the metallic oxide semiconductor layer and the a-Si layer sequentially; and
patterning the metallic oxide semiconductor layer and the a-Si layer, so as to form the first region of the active layer, the first region of the active layer comprising the metallic oxide semiconductor layer and the a-Si layer.

7. The method according to claim 6 , wherein the entire active layer consists of the metallic oxide semiconductor layer and the a-Si layer laminated one another.

8. The method according to claim 7 , wherein the step of forming the source electrode and the drain electrode comprises:
forming a source/drain metal layer on the active layer;
applying a photoresist onto the source/drain metal layer, and exposing and developing the photoresist, so as to form a photoresist fully-reserved region corresponding to a region where the source electrode and the drain electrode are located, a photoresist half-reserved region corresponding to the first region of the active layer, and a photoresist unreserved region corresponding to other regions;
etching off the source/drain metal layer at the photoresist unreserved region;
ashing the photoresist at the photoresist half-reserved region, and etching off the source/drain metal layer and the a-Si layer with a certain thickness at the first region; and
removing the remaining photoresist, so as to form the source electrode and the drain electrode.

9. The method according to claim 6 , wherein the source region and the drain region of the active layer consist of the metallic oxide semiconductor layer as well as the a-Si layer and a heavily-doped a-Si layer sequentially arranged on the metallic oxide semiconductor layer, and the a-Si layer and the heavily-doped a-Si layer are laminated one another.

10. The method according to claim 9 , wherein the step of forming the active layer comprises:
forming the metallic oxide semiconductor layer, the a-Si layer and the heavily-doped a-Si layer sequentially, and patterning the metallic oxide semiconductor layer, the a-Si layer and the heavily-doped a-Si layer so as to form a pattern of the active layer, the entire active layer comprising the metallic oxide semiconductor layer, the a-Si layer and the heavily-doped a-Si layer, and
the step of forming the source electrode and the drain electrode comprises:
forming a source/drain metal layer on the active layer;
applying a photoresist onto the source/drain metal layer, and exposing and developing the photoresist, so as to form a photoresist fully-reserved region corresponding to a region where the source electrode and the drain electrode are located, a photoresist half-reserved region corresponding to the first region of the active layer, and a photoresist unreserved region corresponding to other regions;
etching off the source/drain metal layer at the photoresist unreserved region;
ashing the photoresist at the photoresist half-reserved region, and etching off the source/drain metal layer and the heavily-doped a-Si layer at the first region; and
removing the remaining photoresist, so as to form the source electrode and the drain electrode.

11. The method according to claim 6 , wherein the silicon semiconductor layer consists of a heavily-doped a-Si layer, and the source region and the drain region of the active layer consist of the metallic oxide semiconductor layer and the heavily-doped a-Si layer arranged on the metallic oxide semiconductor layer.

12. The method according to claim 11 , wherein the step of forming the source electrode and the drain electrode comprises:
forming a source/drain metal layer on the active layer;
applying a photoresist onto the source/drain metal layer, and exposing and developing the photoresist, so as to form a photoresist fully-reserved region corresponding to a region where the source electrode and the drain electrode are located, a photoresist half-reserved region corresponding to the first region of the active layer, and a photoresist unreserved region corresponding to other regions;
etching off the source/drain metal layer at the photoresist unreserved region;
ashing the photoresist at the photoresist half-reserved region, and etching off the source/drain metal layer and the heavily-doped a-Si layer with a certain thickness at the first region; and
removing the remaining photoresist, so as to form the source electrode and the drain electrode.

13. The method according to claim 6 , wherein the source region and the drain region of the active layer consist of the metallic oxide semiconductor layer.

14. The method according to claim 13 , wherein the step of forming the active layer comprises:
forming the metallic oxide semiconductor layer;
forming the a-Si layer on the metallic oxide semiconductor layer;
applying a photoresist onto the a-Si layer, and exposing and developing the photoresist, so as to form a photoresist fully-reserved region corresponding to the first

Assignees

• Boe Technology Group Co Ltd
• Chongqing Boe Optoelectronics Tech Co Ltd

Inventors

• Wang Wu
• Qiu Haijun
• Shang Fei
• Wang Guolei

Classifications

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/0321

  comprising silicon, e.g. amorphous silicon or polysilicon · CPC title

• H01L29/66757 Primary

  Electricity · mapped topic

• H01L27/1225

  Electricity · mapped topic

• H01L29/7869

  Electricity · mapped topic