Semiconductor device, method of fabricating the semiconductor device, and method of forming epitaxial layer

Patent metadata

Field	Value
Publication number	US-9653472-B2
Application number	US-201514657663-A
Country	US
Kind code	B2
Filing date	Mar 13, 2015
Priority date	Aug 22, 2014
Publication date	May 16, 2017
Grant date	May 16, 2017

Abstract

According to example embodiments, a method of fabricating a semiconductor device includes alternately stacking interlayer insulating layers and intermediate layers on a substrate, forming openings passing through the interlayer insulating layers and the intermediate layers to form recessed regions in the substrate, forming first epitaxial layers on recessed surfaces in the recessed regions, and forming second epitaxial layers using the first epitaxial layers as seed layers. The second epitaxial layers fill the recessed regions and extend above the substrate.

First claim

What is claimed is:

1. A method of fabricating a semiconductor device, comprising:
alternately stacking interlayer insulating layers and sacrificial layers on a substrate;
forming recessed regions in the substrate, the forming recessed regions including forming openings passing through the interlayer insulating layers and the sacrificial layers;
forming first epitaxial layers on recessed surfaces of the recessed regions;
forming second epitaxial layers using the first epitaxial layers as seed layers, the second epitaxial layers filling the recessed regions and extending above the substrate; and
forming channel layers in the openings on the second epitaxial layers.

2. The method of claim 1 , wherein the first epitaxial layers are formed at a higher temperature and a higher pressure than the second epitaxial layers.

3. The method of claim 1 , wherein the first epitaxial layers are formed at a higher growth rate than the second epitaxial layers.

4. The method of claim 3 , wherein the first epitaxial layers are formed to have a higher density than the second epitaxial layers.

5. The method of claim 1 , wherein the first epitaxial layers and the second epitaxial layers are formed at different temperatures in the range of about 800° C. to about 900° C.

6. The method of claim 1 , wherein the first epitaxial layers have a substantially uniform thickness and do not extend above the substrate.

7. The method of claim 1 , wherein a thickness of the first epitaxial layers is in the range of about 2% to about 9% of a thickness of the second epitaxial layers.

8. The method of claim 7 , wherein the thickness of the first epitaxial layers is in the range of about 3 nm to about 10 nm.

9. The method of claim 1 , further comprising:
cleaning the substrate before forming the first epitaxial layers, wherein
the cleaning the substrate includes using at least one of a germanium-containing material and a chlorine-containing material, and
wherein the cleaning the substrate, the forming the first epitaxial layers, and the forming the second epitaxial layers are performed in-situ.

10. The method of claim 1 , further comprising:
forming gate dielectric layers on the second epitaxial layers along sidewalls of the openings before forming the channel layers, wherein the gate dielectric layers include blocking layers, charge storage layers, and tunneling layers;
forming lateral openings by removing the sacrificial layers;
oxidizing portions of the blocking layers and the second epitaxial layers exposed by the lateral openings; and
forming gate electrodes by filling the lateral openings with a conductive material.

11. The method of claim 10 , wherein the oxidizing portions of the blocking layers and the second epitaxial layers include oxidizing the portions of the second epitaxial layers to form insulating layers between the second epitaxial layers and the gate electrodes.

12. The method of claim 1 , further comprising forming pads in the openings,
wherein the pads are contact with upper portions of the channel layers.

13. The method of claim 12 , further comprising:
forming an additional opening passing through the interlayer insulating layers and the sacrificial layers to expose the sacrificial layers;
removing the exposed sacrificial layers to form lateral opening;
forming gates in the lateral opening;
forming common source line in the additional opening; and
forming bit lines on the pads.

14. A method of fabricating a semiconductor device, comprising:
alternately stacking interlayer insulating layers and intermediate layers on a substrate;
forming recessed regions in the substrate, the forming recessed regions including forming openings passing through the interlayer insulating layers and the intermediate layers;
forming first epitaxial layers on recessed surfaces of the recessed regions;
forming second epitaxial layers in the recessed regions using the first epitaxial layers as seed layers, the second epitaxial layers having a lower density than the first epitaxial layers; and
forming channel layers in the openings on the second epitaxial layers.

15. The method of claim 14 , wherein
the alternately stacking interlayer insulating layers and intermediate layers includes using conductive layers as the intermediate layers to form the interlayer insulating layers and the conductive layers alternately stacked on the substrate; and
the forming recessed regions includes forming openings passing through the interlayer insulating layers and the conductive layers.

16. The method of claim 15 , wherein the first epitaxial layers are formed at a higher temperature and a higher pressure than the second epitaxial layers.

17. The method of claim 15 , further comprising:
forming insulating layers alongside surfaces of the openings on the first epitaxial layers before forming the second epitaxial layers.

18. The method of claim 14 , further comprising:
forming gate dielectric layers in the openings on top of the second epitaxial layers before forming the channel layers; and
forming bit lines on top of the channel layers, wherein the gate dielectric layers are between the channel layers and the interlayer insulating layers.

19. The method of claim 18 , further comprising:
forming lateral openings by removing the intermediate layers; and
forming gate electrodes by filling the lateral openings with a conductive material.

20. The method of claim 14 , wherein the first epitaxial layers are formed using a first selective epitaxial growth (SEG) process operating within a mass transport limited regime, and
the second epitaxial layers are formed using a second SEG process operating in a surface reaction limited regime.

Assignees

• Lee Woong
• Kim Chae Ho
• An Kyong Won
• Lee Joon Suk
• Lee Woo Sung
• Lim Hun Hyeong
• Samsung Electronics Co Ltd

Inventors

• Lee Woong
• Kim Chae Ho
• An Kyong Won
• Lee Joon Suk
• Lee Woo Sung
• Lim Hun Hyeong

Classifications

• H10D30/6728 Primary

  Vertical TFTs · CPC title

• H01L27/11582 Primary

  Electricity · mapped topic

• H01L29/7926

  Electricity · mapped topic

• H01L27/11556

  Electricity · mapped topic

• H01L27/11519

  Electricity · mapped topic