Semiconductor arrangement with protection circuit

Patent metadata

Field	Value
Publication number	US-9653451-B2
Application number	US-201615078303-A
Country	US
Kind code	B2
Filing date	Mar 23, 2016
Priority date	Mar 24, 2015
Publication date	May 16, 2017
Grant date	May 16, 2017

Abstract

A semiconductor arrangement ( 10 ) with an electrostatic discharge (ESD) protection circuit is disclosed. The semiconductor arrangement ( 10 ) comprises a first semiconductor chip ( 20 a ) with a first integrated circuit ( 25 a ) and a second semiconductor chip ( 20 b ) with a second integrated circuit ( 25 b ). The semiconductor arrangement has an ESD protection circuit ( 30 ). The first semiconductor chip ( 20 a ) is isolated otherwise form the second semiconductor chip ( 20 b ) and the first integrated circuit ( 25 a ) is connected to the second integrated circuit ( 25 b ) exclusively via the ESD protection circuit ( 30 ).

First claim

What is claimed is:

1. A semiconductor arrangement, comprising:
a first semiconductor chip with a first integrated circuit and a first partial circuit;
a second semiconductor chip with a second integrated circuit and a second partial circuit; wherein the first partial circuit and the second partial circuit form together an electrostatic discharge (ESD) protection circuit, and wherein the first semiconductor chip is otherwise isolated from the second semiconductor chip and the first integrated circuit is connected to the second integrated circuit exclusively via the ESD protection circuit.

2. The semiconductor arrangement according to claim 1 , wherein the ESD protection circuit is connected between a first ground line on the first semiconductor chip and a second ground line on the second semiconductor chip.

3. The semiconductor arrangement according to claim 1 , wherein the ESD protection circuit is connected between a first supply line on the first semiconductor chip and a second supply line on the second semiconductor chip.

4. The semiconductor arrangement according to claim 1 , wherein the first partial circuit is configured to be substantially identical to the second partial circuit.

5. The semiconductor arrangement according to claim 1 , wherein the ESD protection circuit is integrated in a third semiconductor chip.

6. The semiconductor arrangement according to claim 1 , wherein the ESD protection circuit has two branches and each of the two branches has respectively one diode and one Zener diode, which are connected in series.

7. The semiconductor arrangement according to claim 1 , wherein the first semiconductor chip is stacked onto the second semiconductor chip.

8. The semiconductor arrangement according to claim 1 , wherein the first semiconductor chip is arranged next to the second semiconductor chip.

9. The semiconductor arrangement according to claim 1 , wherein two ESD protection circuits are connected in series between the first integrated circuit and the second integrated circuit.

10. The semiconductor arrangement according to claim 9 , wherein a connector is present between the two ESD protection circuits.

11. The semiconductor arrangement according to claim 1 , wherein the first semiconductor chip and the second semiconductor chip are accommodated in a common housing.

12. A semiconductor arrangement comprising:
a first semiconductor chip with a first integrated circuit;
a second semiconductor chip with a second integrated circuit; and
an electrostatic discharge (ESD) protection circuit;
wherein the first semiconductor chip is otherwise isolated from the second semiconductor chip and the first integrated circuit is connected to the second integrated circuit exclusively via the ESD protection circuit; and
wherein the ESD protection circuit has two branches and each of the two branches has respectively one diode and one Zener diode, which are connected in series.

13. A semiconductor arrangement comprising:
a first semiconductor chip with a first integrated circuit;
a second semiconductor chip with a second integrated circuit; and
an electrostatic discharge (ESD) protection circuit;
wherein the first semiconductor chip is otherwise isolated from the second semiconductor chip and the first integrated circuit is connected to the second integrated circuit exclusively via the ESD protection circuit; and
wherein two ESD protection circuits are connected in series between the first integrated circuit and the second integrated circuit.

Assignees

• Micronas Gmbh
• Tdk-Micronas Gmbh

Inventors

• Schmidt Lothar

Classifications

• H10W90/752

  between stacked chips · CPC title

• H10W90/20

  Configurations of stacked chips · CPC title

• H10W72/01

  Manufacture or treatment · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W42/60

  protecting against electrostatic charges or discharges, e.g. Faraday shields (integrated devices comprising arrangements for electrical protection H10D89/60) · CPC title