Monolithic integration of a III-V optoelectronic device, a filter and a driving circuit

Patent metadata

Field	Value
Publication number	US-9653441-B1
Application number	US-201615187087-A
Country	US
Kind code	B1
Filing date	Jun 20, 2016
Priority date	Jun 20, 2016
Publication date	May 16, 2017
Grant date	May 16, 2017

Abstract

After forming an opening extending through a (100) silicon layer and a buried insulator layer and into a (111) silicon layer of a semiconductor-on-insulator (SOI) substrate, a light-emitting element is formed within the opening. A portion of the (111) silicon layer located beneath the light-emitting element is patterned to form a patterned structure for tuning light emission characteristics and enhancing efficiency of the light-emitting element. Next, at least one field effect transistor (FET) is formed on the (100) silicon layer for driving the light-emitting element.

First claim

What is claimed is:

1. A semiconductor structure comprising:
a semiconductor-on-insulator (SOI) substrate including, from bottom to top, a (111) silicon layer, a buried insulator layer and a (100) silicon layer;
a field effect transistor (FET) located on a portion of the (100) silicon layer;
a light-emitting element separated from the FET and embedded in the SOI substrate, wherein the light-emitting element is laterally surrounded by the (100) silicon layer, the buried insulator layer and an upper portion of the (111) silicon layer; and
a patterned portion of the (111) silicon layer located beneath the light-emitting element, the patterned portion of the (111) silicon layer comprising trenches exposing portions of a bottommost surface of the light-emitting element.

2. The semiconductor structure of claim 1 , wherein a topmost surface of the light-emitting element is coplanar with a top surface of the (100) silicon layer.

3. The semiconductor structure of claim 2 , wherein the light-emitting element comprises, from bottom to top, a first contact layer, a light-emitting layer and a second contact layer, wherein a top surface of the second contact layer is coplanar with the top surface of the (100) silicon layer.

4. The semiconductor structure of claim 3 , wherein each of the first contact layer, the light-emitting layer and the second contact layer has a (111) crystallographic surface orientation.

5. The semiconductor structure of claim 3 , wherein the first contact layer comprises an n-doped III-V compound semiconductor material, and the second contact layer comprises a p-doped III-V compound semiconductor material.

6. The semiconductor structure of claim 5 , wherein the first contact layer comprises Si-doped GaN or Si-doped AlN, and the second contact layer comprises Mg-doped GaN, Mg-doped AlN, Zn-doped GaN, or Zn-doped AlN.

7. The semiconductor structure of claim 3 , wherein the light-emitting layer comprises alternating layers of a first III-V compound semiconductor material and a second III-V compound semiconductor material having a bandgap narrower than the first III-V compound semiconductor material.

8. The semiconductor structure of claim 7 , wherein the light-emitting layer comprises alternating layers of GaN and AlGaN or alternating layers of GaN and InGaN.

9. The semiconductor structure of claim 1 , wherein the FET comprises a gate structure located over a channel region and source/drain regions and laterally surrounding the channel region, wherein the channel region and the source/drain regions are located within the (100) silicon layer.

10. The semiconductor structure of claim 9 , further comprising another FET located on another portion of the (100) silicon layer, wherein the another FET comprises another gate structure located over another channel region located within the (100) silicon layer and another source/drain regions located within the (100) silicon layer and laterally surrounding the another channel region, wherein the another source/drain regions comprises dopant having a conductivity type opposite a conductivity type of dopants in the source/drain regions.

11. A method of forming a semiconductor structure comprising:
forming an opening extending through a (100) silicon layer, a buried insulator layer and into an upper portion of a (110) silicon layer of a semiconductor-on-insulator (SOI) substrate;
forming a light-emitting element within the opening, the light-emitting element having a topmost surface coplanar with a top surface of the (100) silicon layer;
patterning a portion of the (111) silicon layer located beneath the light-emitting element; and
forming a field effect transistor (FET) in a region of the (100) silicon layer.

12. The method of claim 11 , wherein the opening exposes a sub-surface of the (111) silicon layer that is located below a top surface of the (111) silicon layer.

13. The method of claim 12 , wherein the forming the light-emitting element comprises:
forming a first contact layer on the sub-surface of the (111) silicon layer;
forming a light-emitting layer on the first contact layer; and
forming a second contact layer on the light-emitting layer.

14. The method of claim 13 , wherein each of the first contact layer, the light-emitting layer and the second contact layer is formed by a selective epitaxial growth.

15. The method of claim 13 , further comprising forming a first contact structure contacting the first contact layer and forming a second contact structure contacting the second contact layer.

16. The method of claim 11 , wherein the portion of the (111) silicon layer located beneath the light-emitting element is patterned to form a patterned structure comprising features and trenches separating the features from one another.

17. The method of claim 16 , wherein the trenches exposes portions of a bottommost surface of the light-emitting element.

18. The method of claim 11 , wherein the forming the FET in the region of the (100) silicon layer comprises:
forming a gate stack over a portion of the (100) silicon layer;
forming a gate spacer on sidewalls of the gate stack; and
forming source/drain regions in portions of the (100) silicon layer located on opposite sides of the gate stack.

19. The method of claim 18 , wherein the gate stack comprises, from bottom to top, a gate dielectric, a gate electrode and a gate cap.

20. The method of claim 18 , further comprising forming another FET in another region of the (100) silicon layer, wherein the forming the another FET comprises:
forming another gate stack over another portion of the (100) silicon layer;
forming another gate spacer on sidewalls of the another gate stack; and
forming another source/drain regions in portions of the (100) silicon layer located on opposite sides of the another gate stack, wherein the another source/drain regions comprise dopants having a conductivity type opposite to a conductivity type of dopants in the source/drain regions.

Assignees

• IBM

Inventors

• Chen Chia-Yu
• Hung Li-Wen
• Lai Jui-Hsin
• Lee Ko-Tao

Classifications

• H10W90/00 Primary

  Package configurations · CPC title

• H01L29/2003

  Electricity · mapped topic

• H01L25/50

  Electricity · mapped topic

• H01L25/167 Primary

  Electricity · mapped topic

• H01L29/0649

  Electricity · mapped topic