Semiconductor package with adhesive material pre-printed on the lead frame and chip, and its manufacturing method

US9653424B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9653424-B2
Application numberUS-201414526518-A
CountryUS
Kind codeB2
Filing dateOct 29, 2014
Priority dateSep 21, 2009
Publication dateMay 16, 2017
Grant dateMay 16, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

This invention discloses a semiconductor package with adhesive material pre-printed on the lead frame and chip, and the manufacturing method. The adhesive material is applied onto the chip carrier and the pin of the lead frame and also on the front electrode of the semiconductor chip via pre-printing. The back of the semiconductor chip is adhered on the chip carrier, and the front electrode of the semiconductor chip and the pin are connected respectively with a metal connector. The size, shape and thickness of the adhesive material are applied according to different application requirements according to size and shapes of the contact zone of the semiconductor chip and the metal connector. Particularly, the adhesive zones are formed by pre-printing the adhesive material thus significantly enhance the quality and performance of semiconductor products, and improves the productivity.

First claim

Opening claim text (preview).

We claim: 1. A method for manufacturing a semiconductor package comprising: a) printing a conductive adhesive material on a plurality of adhesive zones on a lead frame at a room temperature and simultaneously printing the conductive adhesive material on a plurality of adhesive zones on chip carrier of the lead frame at a room temperature followed by curing the adhesive material; b) printing a conductive adhesive layer on a plurality of electrodes disposed on a top surface of a semiconductor chip followed by mounting a backside opposite the top surface of the semiconductor chip onto the leadframe carrier; c) applying a heating process for adhering the backside of the semiconductor chip onto the adhesive zones of the chip carrier of the lead frame and simultaneously forming metal connectors for interconnecting a plurality of pins disposed on the leadframe to the electrodes disposed on a top surface of the semiconductor chip; and d) molding the leadframe and the semiconductor chip into a plastic package. 2. The manufacturing method of claim 1 wherein the step of printing the plurality of adhesive zones on the chip carrier comprises a step of printing the plurality of adhesive zones with a printable epoxy resin. 3. The manufacturing method of claim 1 wherein the step of printing the plurality of adhesive zones on the chip carrier comprises a step of applying a screen having openings corresponding to the adhesive zones and a plurality of contact pads on the leadframe for screen printing the plurality of adhesive zones with the conductive adhesive material having substantially a same thickness as the screen. 4. The manufacturing method of claim 1 wherein the step of printing the conductive adhesive layer on the plurality of electrodes on the top surface of the semiconductor chip comprises a step of applying a screen having openings corresponding to the plurality of electrodes on the top surface of the semiconductor chip for screen printing the adhesive conductive layer on the electrodes with the conductive adhesive material having substantially a same thickness as the screen. 5. The manufacturing method of claim 1 wherein the step of printing the plurality of adhesive zones on the chip carrier comprises a step of printing one of the adhesive zones on the chip carrier having an outer profile having a substantially same size and shape as a shape and size of the semiconductor chip. 6. The manufacturing method of claim 1 wherein the step of printing the plurality of adhesive zones on the chip carrier comprises a step of printing the adhesive zones on the chip carrier having an outer profile having a substantially same size and shape as a shape and size of the chip carrier. 7. The manufacturing method of claim 1 wherein the step of printing the plurality of adhesive zones on the chip carrier comprises a step of printing the adhesive zones on the chip carrier having an outer profile smaller than a size of the semiconductor chip. 8. The manufacturing method of claim 1 wherein the step of printing a conductive adhesive material on a plurality of adhesive zones on a lead frame further comprising a step of printing the conductive adhesive material on the plurality of pins of said leadframe. 9. The manufacturing method of claim 1 wherein the step simultaneously forming the metal connectors for interconnecting the plurality of pins on the leadframe to the electrodes disposed on a top surface of the semiconductor chip further comprising a step of securely connecting the pins on the leadframe with a metal clip or metal ribbon to the electrodes disposed on the top surface of the semiconductor chip. 10. A method for manufacturing a semiconductor package comprising: a) printing a conductive adhesive material on a plurality of adhesive zones on a lead frame at a room temperature and simultaneously printing the conductive adhesive material on a plurality of adhesive zones on chip carrier of the lead frame at a room temperature followed by curing the adhesive material and wherein the step of printing the plurality of adhesive zones on the chip carrier comprises a step of printing one of the adhesive zones on the chip carrier having an outer profile having a substantially same size and shape as a shape and size of the semiconductor chip; b) printing a conductive adhesive layer on a plurality of electrodes disposed on a top surface of a semiconductor chip followed by mounting a backside opposite the top surface of the semiconductor chip onto the leadframe carrier; c) applying a heating process for adhering the backside of the semiconductor chip onto the adhesive zones of the chip carrier of the lead frame and simultaneously forming metal connectors for interconnecting a plurality of pins disposed on the leadframe to the electrodes disposed on a top surface of the semiconductor chip; and d) molding the leadframe and the semiconductor chip into a plastic package. 11. The manufacturing method of claim 10 wherein the step of printing the plurality of adhesive zones on the chip carrier comprises a step of printing the plurality of adhesive zones with a printable epoxy resin. 12. A method for manufacturing a semiconductor package comprising: a) printing a conductive adhesive material on a plurality of adhesive zones on a lead frame at a room temperature and simultaneously printing the conductive adhesive material on a plurality of adhesive zones on chip carrier of the lead frame at a room temperature followed by curing the adhesive material and wherein the step of printing the plurality of adhesive zones on the chip carrier comprises a step of printing the adhesive zones on the chip carrier having an outer profile having a substantially same size and shape as a shape and size of the chip carrier; b) printing a conductive adhesive layer on a plurality of electrodes disposed on a top surface of a semiconductor chip followed by mounting a backside opposite the top surface of the semiconductor chip onto the leadframe carrier; c) applying a heating process for adhering the backside of the semiconductor chip onto the adhesive zones of the chip carrier of the lead frame and simultaneously forming metal connectors for interconnecting a plurality of pins disposed on the leadframe to the electrodes disposed on a top surface of the semiconductor chip; and d) molding the leadframe and the semiconductor chip into a plastic package. 13. The manufacturing method of claim 12 wherein the step of printing the plurality of adhesive zones on the chip carrier comprises a step of printing the plurality of adhesive zones with a printable epoxy resin. 14. A method for manufacturing a semiconductor package comprising: a) printing a conductive adhesive material on a plurality of adhesive zones on a lead frame at a room temperature and simultaneously printing the conductive adhesive material on a plurality of adhesive zones on chip carrier of the lead frame at a room temperature followed by curing the adhesive material and wherein the step of printing the plurality of adhesive zones on the chip carrier comprises a step of printing the adhesive zones on the chip carrier having an outer profile smaller than a size of the semiconductor chip; b) printing a conductive adhesive layer on a plurality of electrodes disposed on a top surface of a semiconductor chip followed by mounting a backside opposite the top surface of the semiconductor chip onto the leadframe carrier; c) applying a heating process for adhering the backside of the semiconductor chip onto the adhesive zones of the chip carrier of the lead frame and simultaneously forming metal connectors for interconnecting a plurality of pins

Assignees

Inventors

Classifications

  • between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

  • between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

  • Encapsulations, e.g. protective coatings · CPC title

  • using a polymer adhesive, e.g. an adhesive based on silicone or epoxy · CPC title

  • Compression bonding, e.g. thermocompression bonding · CPC title

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Frequently asked questions

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What does patent US9653424B2 cover?
This invention discloses a semiconductor package with adhesive material pre-printed on the lead frame and chip, and the manufacturing method. The adhesive material is applied onto the chip carrier and the pin of the lead frame and also on the front electrode of the semiconductor chip via pre-printing. The back of the semiconductor chip is adhered on the chip carrier, and the front electrode of …
Who is the assignee on this patent?
Alpha & Omega Semiconductor Incorporated, Alpha & Omega Semiconductor
What technology area does this patent fall under?
Primary CPC classification H10W70/421. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue May 16 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).