Semiconductor device and method of manufacturing semiconductor device

Patent metadata

Field	Value
Publication number	US-9653304-B2
Application number	US-201514937367-A
Country	US
Kind code	B2
Filing date	Nov 10, 2015
Priority date	Nov 14, 2014
Publication date	May 16, 2017
Grant date	May 16, 2017

Abstract

A method of manufacturing a semiconductor device includes forming a first gate member on a semiconductor substrate through a gate insulating film, forming a spacer on the first gate member, flattening a surface of the spacer, forming a first gate by partially etching the first gate member using the spacer as a mask, forming a second gate member so as to cover the first gate and the spacer having the flattened surface, forming a first insulating film on a surface of the second gate member, and forming a second gate by causing the second gate member to retreat while removing the first insulating film by etching.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device comprising:
forming a first gate member on a semiconductor substrate through a gate insulating film;
forming a spacer on the first gate member;
flattening a surface of the spacer;
forming a first gate by partially etching the first gate member using the spacer as a mask;
forming a second gate member so as to cover the first gate and the spacer having the flattened surface;
forming a first insulating film on a surface of the second gate member, after the second gate member is formed; and
forming a second gate by causing the second gate member to retreat while removing the first insulating film by etching.

2. The manufacturing method according to claim 1 , further comprising:
forming a second insulating film so as to cover the second gate;
forming a side wall, which abuts a side surface of the second gate, by causing the second insulating film to retreat by etching; and
forming a metal compound layer on an upper surface of the second gate after the side wall is formed.

3. The manufacturing method according to claim 1 ,
wherein flattening the surface of the spacer is performed by chemical mechanical polishing.

4. The manufacturing method according to claim 1 ,
wherein, in flattening the surface of the spacer, the surface of the spacer is processed so as to be substantially parallel to a principal plane of the semiconductor substrate.

5. The manufacturing method according to claim 1 , further comprising:
forming a mask which includes an opening on the first gate member,
wherein forming the spacer includes forming a spacer member so as to fill the opening, and causing the spacer member to retreat by etching.

6. The manufacturing method according to claim 1 , further comprising:
forming a source and a drain at positions between which the first gate and the second gate of the semiconductor substrate are interposed.

7. The manufacturing method according to of claim 6 ,
wherein the first insulating film constitutes a gate insulating film of a semiconductor element other than a semiconductor element including the first gate, the second gate, the source, and the drain.

8. The manufacturing method according to claim 2 , further comprising:
forming a source and a drain at positions between which the first gate and the second gate of the semiconductor substrate are interposed; and
forming a source wiring which is electrically connected to the source,
wherein, in forming the metal compound layer on the upper surface of the second gate, the metal compound layer is formed on an upper surface of the source wiring and an upper surface of the drain.

9. The manufacturing method according to claim 5 ,
wherein the spacer includes a pair of spacer pieces which are disposed to be separated in the opening, and
the method further comprises:
forming a source and a drain at positions between which the first gate and the second gate of the semiconductor substrate are interposed;
forming a wiring material which is electrically connected to the source so as to fill a gap between the pair of spacer pieces; and
forming a source wiring by etching the wiring material such that a height of an upper surface of the source wiring is lower than a height of the spacer before the surface of the spacer is flattened.

Assignees

• Lapis Semiconductor Co Ltd

Inventors

• Chiba Akira

Classifications

• H10P95/062

  involving a dielectric removal step · CPC title

• H10P50/71

  using masks for conductive or resistive materials · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H01L21/32139

  Electricity · mapped topic

• H01L21/31053

  Electricity · mapped topic