In-memory computational device

Patent metadata

Field	Value
Publication number	US-9653166-B2
Application number	US-201615206278-A
Country	US
Kind code	B2
Filing date	Jul 10, 2016
Priority date	Nov 28, 2013
Publication date	May 16, 2017
Grant date	May 16, 2017

Abstract

A computing device includes a memory array built of several sections having memory cells arranged in rows and column, at least one cell in each column of the memory array being connected to a bit line; and at least one multiplexer to connect a bit line in a first column of a first section to a bit line in a second column in a second section different from the first section, where the second column is not continuous with the first column ; and a decoder to activate at least two word lines of the first section and a word line connected to a cell in the second column in the second section to write a bit line voltage associated with a result of a logical operation performed on the first column into the cell in the second column.

First claim

What is claimed is:

1. A computing device comprising:
a memory array comprising a plurality of sections having memory cells arranged in rows and column, at least one cell in each column of said memory array being connected to a bit line; at least one multiplexer to connect a bit line in a first column of a first section to a bit line in a second column in a second section different from said first section, wherein said second column is not continuous with said first column; and
a decoder to activate at least two word lines of said first section and a word line connected to a cell in said second column in said second section to write a bit line voltage associated with a result of a logical operation performed on said first column into said cell in said second column.

2. A computing device according to claim 1 further comprising a controller to provide said decoder with an instruction set for decoding in said decoder.

3. A computing device according to claim 2 wherein said instruction set is of a small size.

4. A computing device according to claim 3 wherein said instruction set from said controller comprises a maximum size of 64 bits.

5. A computing device according to claim 2 wherein said instruction set represents compressed data associated with the operation of any one of said memory array, said at least one multiplexer, and said decoder.

6. A computing device according to claim 5 wherein said decoder decompresses said compressed data.

7. A computing device according to claim 1 wherein said decoder activates said at least one multiplexer to connect said bit lines in said first section and said second section.

8. A computing device according to claim 1 wherein said decoder simultaneously accesses a plurality of read word lines and write word lines in said memory array.

9. A computing device according to claim 2 wherein said decoder decodes said instruction set from said controller into an instruction set for accessing in parallel a plurality of read word lines and write word lines in said memory array.

10. A computing device according to claim 1 wherein said decoder comprises a memory array comprising a plurality of memory cells arranged in rows and column, at least one cell in each column connected to a bit line having a bit line voltage associated with a logical 1 or a logical 0.

11. A computing device according to claim 10 wherein activation of said word line is through said bit line in said decoder.

12. A computing device according to claim 1 wherein said at least one cell connected to a bit line comprises only one memory cell in each column.

13. A computing device according to claim 1 wherein said at least one cell connected to a bit line comprises all the memory cells in each column.

14. A computing device according to claim 1 wherein said memory cells comprise non-destructive cells.

15. A computing device according to claim 1 wherein said memory cells comprise volatile memory cells.

16. A method of performing in-memory computations in a memory array comprising a plurality of sections having memory cells arranged in rows and column, at least one cell in each column of said memory array being connected to a bit line, the method comprising:
connecting a bit line in a first column of a first section to a bit line in a second column in a second section different from said first section wherein said second column is not continuous with said first column; and
activating at least two word lines of said first section and a word line connected to a cell in said second column in said second section to write a bit line voltage associated with a result of a logical operation performed on said first column into said cell in said second column.

17. A method according to claim 16 further comprising decompressing compressed data represented by a small size instruction set into a large size instruction set.

18. A method according to claim 16 further comprising simultaneously accessing a plurality of read word lines and write word lines.

19. A method according to claim 16 further comprising decoding an instruction set from a controller into an instruction set comprising a plurality of read and write commands.

20. A method according to claim 16 further comprising activating said word line with a bit line voltage.

Assignees

• Gsi Technology Inc

Inventors

• Akerib Avidan
• Ehrman Eli

Classifications

• G11C8/10 Primary

  Decoders · CPC title

• G11C7/1051

  Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits · CPC title

• G11C7/1006

  Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor · CPC title

• G11C15/04 Primary

  using semiconductor elements · CPC title

• G11C7/1012

  Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating · CPC title