Phase hysteretic magnetic josephson junction memory cell

Patent metadata

Field	Value
Publication number	US-9653153-B2
Application number	US-201615013687-A
Country	US
Kind code	B2
Filing date	Feb 2, 2016
Priority date	Mar 11, 2015
Publication date	May 16, 2017
Grant date	May 16, 2017

Abstract

One embodiment describes a memory cell. The memory cell includes a phase hysteretic magnetic Josephson junction (PHMJJ) that is configured to store one of a first binary logic state corresponding to a binary logic-1 state and a second binary logic state corresponding to a binary logic-0 state in response to a write current that is provided to the memory cell and to generate a superconducting phase based on the stored digital state. The memory cell also includes a superconducting read-select device that is configured to implement a read operation in response to a read current that is provided to the memory cell. The memory cell further includes at least one Josephson junction configured to provide an output based on the superconducting phase of the PHMJJ during the read operation, the output corresponding to the stored digital state.

First claim

What is claimed is:

1. A memory cell comprising:
a magnetic memory storage device that is configured to store one of a first binary logic state corresponding to a binary logic-1 state and a second binary logic state corresponding to a binary logic-0 state in response to a write current that is provided to the memory cell;
a magnetic-barrier Josephson junction (MBJJ) that is configured to implement a read operation in response to a read current that is provided to the memory cell; and
at least one Josephson junction configured to provide an output corresponding to the stored digital state.

2. The memory cell of claim 1 , wherein the magnetic memory storage device is further to generate a first magnetic state based on the stored digital state, and wherein the MBJJ is configured to provide a second magnetic state in response to the read current to trigger the at least one Josephson junction.

3. The memory cell of claim 2 , wherein the second magnetic state circulates in a first loop through the MBJJ and the at least one Josephson junction in response to the MBJJ being in the π-state, and the first magnetic state circulates in a second loop through the magnetic memory storage device and the at least one Josephson junction in response to the magnetic memory storage device being in the π-state.

4. The memory cell of claim 3 , wherein the read current comprises a first read current and a second read current that are both provided to the memory cell during a read operation, wherein the first read current is provided to a node interconnecting the MBJJ and the magnetic memory storage device to bias the at least one Josephson junction and the second read current is inductively coupled to the MBJJ to switch the MBJJ from a zero-state to the π-state to provide the second magnetic state.

5. The memory cell of claim 4 , wherein a magnitude the second magnetic state is based on an internal superconductor flux quantum divided by an inductance term.

6. The memory cell of claim 1 , wherein the MBJJ and the magnetic memory storage device are arranged in parallel with respect to each other in the memory cell, and wherein the at least one Josephson junction comprises a pair of Josephson junctions that are arranged in series with respect to the MBJJ and the magnetic memory storage device to form a Superconducting Quantum Interference Device (SQUID).

7. The memory cell of claim 1 , wherein the magnetic memory storage device is configured to generate the magnetic state in response to storing one of the first and second binary logic states, wherein the magnetic memory storage device is configured to trigger the at least one Josephson junction during the read operation based on the magnetic state, the read current, and a superconducting read-select device to provide a voltage having a first magnitude at an output of the memory cell, the first magnitude of the voltage being indicative of the one of the first and second binary logic states.

8. The memory cell of claim 7 , wherein the magnetic memory storage device is configured to generate a zero superconducting phase in response to storing the other of the first and second binary logic states, wherein the magnetic memory storage device is configured to not trigger the at least one Josephson junction during the read operation based on the zero superconducting phase, such that a voltage having a second magnitude is provided at the output, the second magnitude of the voltage being indicative of the other of the first and second binary logic states.

9. A Josephson magnetic random access memory (JMRAM) system comprising an array of memory cells comprising the memory cell of claim 1 , the array of memory cells being arranged in rows and columns, wherein the write current is a word-write current that is provided on a word-write line associated with a row of the array of memory cells, wherein a second write current is provided on a bit-write line of the array of memory cells as a bit-write current, wherein the read current is a word-read current that is provided on a word-read line associated with the row of the array of memory cells, and wherein a second read current is provided on a bit-read line as a bit-read current.

10. The JMRAM of claim 9 , wherein the word-write line and the word-read line are common to each of the memory cells in a given row of the array, and wherein the bit-write line and the bit-read line are common to each of the memory cells in a given column of the array, such that the array of memory cells are arranged in series with respect to each of the rows and each of the columns of the array.

11. The JMRAM of claim 9 , wherein each of the word-write line and the bit-write line associated with a given memory cell are magnetically coupled to the magnetic memory storage device, wherein the word-write current is provided on the word-write line through each of the memory cells in a given one of the rows during a data write operation, and wherein the bit-write line comprises a plurality of bit-write lines that are each associated with a respective one of the columns, each of a respective plurality of bit-write currents being associated with storage of one of the binary logic-1 state and the binary logic-0 state in each of the memory cells in the given one of the rows.

12. The JMRAM of claim 9 , wherein the word-read line comprises a plurality of word-read lines that are each associated with a respective one of the rows, each of the plurality of word-read lines being inductively coupled to a superconducting read-select device associated with each of the respective memory cells in a given one of the rows, wherein the bit-read line comprises a plurality of bit-read lines that are each associated with a respective one of the columns and are provided to bias the at least one Josephson junction associated with each of the respective memory cells in a given one of the rows that is selected in response to the word-read current during the read operation to provide an indication of the stored digital state of each of the magnetic memory storage devices in the given one of the rows on the plurality of bit-read lines.

13. The memory cell of claim 1 , wherein the magnetic memory storage device is a phase hysteretic magnetic Josephson junction (PHMJJ).

Assignees

• Herr Anna Y
• Herr Quentin P
• Miklich Andrew Hostetler
• Northrop Grumman Systems Corp

Inventors

• Herr Anna Y
• Herr Quentin P
• Miklich Andrew Hostetler

Classifications

• G11C11/44 Primary

  using super-conductive elements, e.g. cryotron · CPC title

• G11C11/16

  using elements in which the storage effect is based on magnetic spin effect · CPC title