Electronic apparatus

Patent metadata

Field	Value
Publication number	US-9652702-B2
Application number	US-201615152983-A
Country	US
Kind code	B2
Filing date	May 12, 2016
Priority date	May 29, 2015
Publication date	May 16, 2017
Grant date	May 16, 2017

Abstract

In an electronic apparatus in which a plurality of controller chips are cascade-connected, if an error occurs in a given chip, the present invention allows at least chips on the upstream side of the error chip to share the existence of the error chip. The electronic apparatus of this invention includes a plurality of control chips which are cascade-connected. Each control chip includes a watchdog timer, and a transfer unit configured to supply, to a second another control chip positioned on the upstream side, as an interrupt signal from the watchdog timer, an OR signal of an interrupt signal generated by the watchdog timer and an interrupt signal generated by another watchdog timer in a first another control chip positioned on the downstream side.

First claim

What is claimed is:

1. An electronic apparatus comprising a plurality of control chips, where the plurality of control chips are cascade-connected,
wherein each control chip comprises:
a watchdog timer; and
a transfer unit configured to supply, to a second another control chip positioned on an upstream side, as an interrupt signal from the watchdog timer, an OR signal of an interrupt signal generated by the watchdog timer and an interrupt signal generated by another watchdog timer in a first another control chip positioned on a downstream side.

2. The apparatus according to claim 1 , wherein if the watchdog timer of each of the control chip generates an interrupt signal, each control chip resets itself and a control chip positioned on the downstream side.

3. The apparatus according to claim 1 , wherein each control chip comprises a reset controller configured to, when the watchdog timer of each of the control chip generates an interrupt signal, reset each of the control chip after an elapse of a preset time.

4. The apparatus according to claim 1 , wherein each control chip comprises a notifying unit configured to, when receiving an interrupt signal from a control chip on the downstream side, notify a CPU of each of the control chip of the reception of the interrupt signal.

5. The apparatus according to claim 1 , wherein each control chip comprises a communication unit configured to communicate with another control chip.

6. The apparatus according to claim 1 , wherein a control chip positioned on a most upstream side performs a process of receiving printing data from an external device, and at least one control chip positioned on the downstream side performs a printing process based on the printing data received via the communication unit.

7. The apparatus according to claim 6 , wherein when receiving an interrupt signal from the control chip on the downstream side, the control chip on the most upstream side stops power supply for driving a head and a motor participating in printing.

Assignees

• Canon Kk

Inventors

• Fujimoto Kazushi

Classifications

• B41J2/04541

  Specific driving circuit · CPC title

• G06K15/408 Primary

  Handling exceptions, e.g. faults (computer driven error handling and recovery for a printer G06F3/1234) · CPC title

• G06F11/0757

  by exceeding a time limit, i.e. time-out, e.g. watchdogs · CPC title

• G06K15/16

  Means for paper feeding or form feeding · CPC title

• G06K15/102

  using ink jet print heads · CPC title