Cooperative flash memory control

Patent metadata

Field	Value
Publication number	US-9652376-B2
Application number	US-201313767723-A
Country	US
Kind code	B2
Filing date	Feb 14, 2013
Priority date	Jan 28, 2013
Publication date	May 16, 2017
Grant date	May 16, 2017

Abstract

This disclosure provides for host-controller cooperation in managing NAND flash memory. The controller maintains information for each erase unit which tracks memory usage. This information assists the host in making decisions about specific operations, for example, initiating garbage collection, space reclamation, wear leveling or other operations. For example, metadata can be provided to the host identifying whether each page of an erase unit has been released, and the host can specifically then command each of consolidation and erase using direct addressing. By redefining host-controller responsibilities in this manner, much of the overhead association with FTL functions can be substantially removed from the memory controller, with the host directly specifying physical addresses. This reduces performance unpredictability and overhead, thereby facilitating integration of solid state drives (SSDs) with other forms of storage. The disclosed techniques are especially useful for direct-attached and/or network-attached storage.

First claim

We claim:

1. A memory controller to interact with a memory having at least one memory array, the at least one memory array having physical storage locations, the memory controller comprising:
at least one interface to receive memory commands from a host and to exchange data in association with the memory commands between a host and the at least one memory array;
logic operable to store in a management table information for every physical storage location of the at least one memory array, the information for each physical storage location representing at least one of operability of memory cells within the physical storage location, wear of memory cells within the physical storage location, period since last programming of valid data within the physical storage location, or validity status of any data stored within the physical storage location; and
logic operable to send to a host information regarding at least one of the physical storage locations of the at least one memory array in dependence on the information retained in the management table;
where the information to be sent to the host by the logic operable to send includes at least one of
state of the at least one of the physical storage locations of the at least one memory array, wherein the state is not data values stored in the at least one memory array, or
an identification of one or more addresses corresponding to at least one of the physical storage locations that match a particular state condition.

2. The memory controller of claim 1 , where the memory controller is embodied in a first integrated circuit, where the at least one interface is embodied as at least one first interface, and where the memory controller further comprises a second interface operable to exchange the data with at least one memory integrated circuit in association with the memory commands.

3. The memory controller of claim 1 , where the memory is flash memory, where each physical storage location includes at least one page of flash memory and where the memory controller is embodied as a flash memory controller.

4. The memory controller of claim 3 , where each physical storage location is exactly equal in size to an erase unit of NAND flash memory.

5. The memory controller of claim 4 , where the information stored in the management table for each physical storage location includes page release information for the respective physical storage location.

6. The memory controller of claim 4 , where the memory controller is to store information in the management table respective to each physical page of memory cells for each erase unit of the at least one memory array.

7. The memory controller of claim 4 , where the information stored in the management table for each physical storage location includes page release information for each page of plural pages in the respective physical storage location.

8. The memory controller of claim 1 , where the information stored in the management table further includes metadata retained in the storage for each physical storage location, the metadata including a physical-to-logical mapping for data stored in the respective physical storage location.

9. The memory controller of claim 1 , where the memory controller further comprises logic operable to receive a command that requests provision of information regarding at least one physical storage location of the memory array to a requesting host in dependence on the information stored in the management table, and where the logic operable to send the information to the host is operable to send the information regarding at least one physical storage location of the memory array to the requesting host in response to the command from the requesting host.

10. The memory controller of claim 9 , where the logic operable to receive a command is operable to receive an asynchronous command, and where the memory controller is operable in response to the asynchronous command to establish at least one condition precedent prior to sending the requested information to the requesting host.

11. The memory controller of claim 10 , where the logic operable to receive a command from the requesting host is further operable to receive a synchronous command from the requesting host, and where the memory controller is operable to send the requested information to the requesting host subject to at least one condition precedent in dependence on whether a command requesting the information regarding the at least one physical storage location of the memory array was a synchronous command type or an asynchronous command type.

12. The memory controller of claim 1 , where the information stored in the management table for each physical storage location includes information indicating at least one of:
whether the respective physical storage location has been marked as bad;
number of erase operations performed on the respective physical storage location; or
information representing page usage for all pages within the respective physical storage location.

13. The memory controller of claim 1 , further comprising logic operable to interpret commands received from a requesting host via an interface of the at least one interface, where the commands received from the requesting host via the interface are compatible with a Nonvolatile Memory Express (NVMe) standard.

14. The memory controller of claim 1 , where the logic operable to send the information to the host is operable to send the information in a manner that is not concurrently solicited.

15. The memory controller of claim 1 , where the memory controller further comprises logic operable to perform for a given physical storage location a comparison with a threshold of at least one of (a) the information stored in the management table for the given physical storage location or (b) information derived from the information stored in the management table for the given physical storage location, and where the logic operable to send the information further comprises logic operable to generate an alert for a host responsive to the comparison.

16. The memory controller of claim 1 , where the logic operable to send the information to the host is operable to send to the host information representing plural ones of the physical storage locations.

17. The memory controller of claim 16 , where:
the information stored in the management table for each respective physical storage location includes information representing validity status of any data stored within the physical storage location;
the information representing validity status includes information identifying page utilization corresponding to the respective physical storage location; and
the information representing the plural ones of the physical storage locations is sufficient to identify candidate physical storage locations for space consolidation in dependence on whether, for each respective physical storage location, the information representing page utilization indicates that page utilization satisfies a threshold condition.

18. The memory controller of claim 17 , where the information representing plural ones of the physical storage locations is sufficient to indicate an ordered list of at least two of the physical storage locations of the at least one memory array in order of increasing page utilization.

19. The memory controller of claim 1 , where:
the information stored in the management table for each respective physical storage location includes information representing validity status of any data stored within the physical storage location;
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Assignees

• Radian Memory Systems Inc

Inventors

• Kuzmin Andrey V
• Jadon Mike
• Mathews Richard M

Classifications

• G11C16/102

  External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators · CPC title

• G06F2212/7207

  management of metadata or control data · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F2212/2022

  Flash memory · CPC title

• G06F12/0246 Primary

  in block erasable memory, e.g. flash memory · CPC title