Software-assisted instruction level execution preemption

Patent metadata

Field	Value
Publication number	US-9652282-B2
Application number	US-201113291476-A
Country	US
Kind code	B2
Filing date	Nov 8, 2011
Priority date	Nov 8, 2011
Publication date	May 16, 2017
Grant date	May 16, 2017

Abstract

One embodiment of the present invention sets forth a technique for instruction level execution preemption. Preempting at the instruction level does not require any draining of the processing pipeline. No new instructions are issued and the context state is unloaded from the processing pipeline. Any in-flight instructions that follow the preemption command in the processing pipeline are captured and stored in a processing task buffer to be reissued when the preempted program is resumed. The processing task buffer is designated as a high priority task to ensure the preempted instructions are reissued before any new instructions for the preempted context when execution of the preempted context is restored.

First claim

The invention claimed is:

1. A method of preempting execution of program instructions in a multi-threaded system, the method comprising:
executing program instructions in a processing pipeline within the multi-threaded system as a first task metadata (TMD) using a first context;
preempting execution using the first context to execute different program instructions in the multi-threaded system using a second context;
invoking a preemption-restore kernel that encodes a preemption restore processing task as a second task metadata (TMD) for execution using the first context when the first context is restored; and
executing the different program instructions in the processing pipeline using the second context.

2. The method of claim 1 , wherein the preemption-restore kernel is configured to store a portion of first context state that is maintained within the processing pipeline during execution of the program instructions using the first context in a context buffer.

3. The method of claim 2 , further comprising preempting execution of the different program instructions to resume execution of the program instructions using the portion of the first context state.

4. The method of claim 2 , further comprising:
invoking the preemption-restore kernel to restore the portion of the first context state to the processing pipeline; and
resuming execution of the program instructions using the portion of the first context state.

5. The method of claim 1 , wherein the preemption-restore kernel is also configured to set up a call stack to execute a routine after the program instructions are executed.

6. The method of claim 5 , wherein execution of the routine frees memory allocated for storing the second TMD.

7. The method of claim 1 , further comprising storing an indication that execution of the program instructions using the first context was preempted.

8. The method of claim 1 , further comprising setting a priority level of the second TMD to a highest priority level.

9. The method of claim 1 , further comprising:
determining, before executing the different program instructions, that the processing pipeline is idle; and
resetting the processing pipeline without storing context state maintained in the processing pipeline for the first context.

10. A non-transitory computer-readable storage medium storing instructions that, when executed by a processor, cause the processor to preempt execution of program instructions in a multi-threaded system, by performing the steps of:
executing program instructions in a processing pipeline within the multi-threaded system as a first task metadata (TMD) using a first context;
preempting execution using the first context to execute different program instructions in the multi-threaded system using a second context;
invoking a preemption-restore kernel that encodes a preemption restore processing task as a second task metadata (TMD) for execution using the first context when the first context is restored; and
executing the different program instructions in the processing pipeline using the second context.

11. A multi-threaded system for preempting execution of program instructions, the multi-threaded system comprising:
a memory configured to store program instruction corresponding to a first context and different program instructions corresponding to a second context;
a host interface coupled to a processing pipeline and configured to preempt execution of the program instructions using the first context to execute different program instructions using a second context; and
the processing pipeline configured to:
execute the program instructions as a first task metadata (TMD) using the first context;
preempt execution of the program instructions using the first context to execute the different program instructions using the second context;
invoke a preemption-restore kernel that encodes a preemption restore processing task as a second task metadata for execution using the first context when the first context is restored; and
execute the different program instructions using the second context.

12. The multi-threaded system of claim 11 , wherein the processing pipeline is further configured by the preemption-restore kernel to, before executing the different program instructions, store a portion of first context state that is maintained within the processing pipeline during the execution of the program instructions using the first context.

13. The multi-threaded system of claim 12 , wherein the host interface is further configured to preempt execution of the different program instructions to resume execution of the program instructions using the portion of the first context state.

14. The multi-threaded system of claim 12 , wherein the processing pipeline is further configured to:
invoke the preemption-restore kernel to restore the portion of the first context state; and
resume execution of the program instructions using the portion of the first context state.

15. The multi-threaded system of claim 12 , wherein the processing pipeline is further configured by the preemption-restore kernel to set up a call stack to execute a routine after the program instructions are executed.

16. The multi-threaded system of claim 15 , wherein execution of the routine frees a portion of the memory allocated for storing the second TMD.

17. The multi-threaded system of claim 15 , wherein the processing pipeline is further configured to store an indication that execution of the program instructions using the first context was preempted.

18. The multi-threaded system of claim 11 , wherein the processing pipeline is further configured by the preemption-restore kernel to store first context state for each thread group executing in a streaming multiprocessor that is preempted in the memory.

19. The multi-threaded system of claim 11 , wherein the processing pipeline is further configured to:
determine, before executing the different program instructions, that the processing pipeline is idle; and
reset the processing pipeline without storing context state maintained in the processing pipeline for the first context.

20. The multi-threaded system of claim 11 , wherein the processing pipeline is further configured by the preemption-restore kernel to restore second context state corresponding to the second context to the processing pipeline before executing the different program instructions.

Assignees

• Cuadra Philip Alexander
• Lamb Christopher
• Shah Lacky V
• Nvidia Corp

Inventors

• Cuadra Philip Alexander
• Lamb Christopher
• Shah Lacky V

Classifications

• G06F9/3861

  Recovery, e.g. branch miss-prediction, exception handling (error detection or correction G06F11/00) · CPC title

• G06F9/3846

  using static prediction, e.g. branch taken strategy · CPC title

• G06F9/46

  Multiprogramming arrangements · CPC title

• G06F9/461 Primary

  Saving or restoring of program or task context · CPC title

• G06F9/3844

  using dynamic branch prediction, e.g. using branch history tables · CPC title