Instruction and logic for support of code modification

Patent metadata

Field	Value
Publication number	US-9652268-B2
Application number	US-201414229161-A
Country	US
Kind code	B2
Filing date	Mar 28, 2014
Priority date	Mar 28, 2014
Publication date	May 16, 2017
Grant date	May 16, 2017

Abstract

A processor includes support for executing binary-translated code including code modifications. The processor includes a processor core that includes a cache to store translation indicators from a physical map, each translation indicator to indicate whether a corresponding memory location includes translated code to be protected. The processor core also includes logic to execute a translated instruction. The translated instruction is translated from an instruction stored in a memory location. The processor core further includes logic to set a translation indicator in the cache corresponding to the memory location to indicate that it includes translated code to be protected. The processor core also includes logic to request senior store buffer drains of other processor cores of the processor based upon the execution of the translated instruction.

First claim

What is claimed is:

1. A processor, comprising:
a first one of a plurality of processor cores, including:
a first cache including circuitry to store one or more translation indicators from a physical map, each translation indicator to indicate whether a corresponding memory location includes translated code to be protected; and
circuitry to:
execute a translated instruction, the translated instruction translated from an instruction stored in a first memory location;
set a first translation indicator in the first cache corresponding to the first memory location to indicate that the first memory location includes translated code to be protected; and
request senior store buffer drains of one or more other ones of the plurality of processor cores of the processor based upon the execution of the translated instruction, the senior store buffers including store operations that have been dispatched, executed, or retired, but that have not been committed.

2. The processor of claim 1 , wherein the first processor core further includes circuitry to:
wait for an acknowledgment of the request for senior store buffer drains; and
write results of the translation to a second memory location based upon the acknowledgment.

3. The processor of claim 1 , wherein the first processor core further includes circuitry to:
compare bytes of the first memory location when the translated execution was executed with bytes of the first memory location after the request for senior store buffer drains; and
write contents of the translation to a second memory location based upon the comparison of the bytes.

4. The processor of claim 1 , wherein:
the processor further comprises a second processor core including a second cache; and
the first processor core includes circuitry to allow incoherence between the first cache and the second cache with respect to whether the first memory location includes translated code to be protected.

5. The processor of claim 1 , wherein:
the processor further comprises a second processor core including a second cache; and
the first processor core includes circuitry to:
set a second translation indicator, the second translation indicator to indicate whether a second memory location includes translated code to be protected; and
invalidate the second translation indicator in caches of the processor based upon setting the second translation indicator.

6. The processor of claim 1 , wherein the first processor core includes circuitry to:
receive a fault from an attempt to store to a memory location with a set translation indicator;
store information about the attempt to a log based upon the fault;
cause an operation for an associated portion of the physical map for the second memory location based upon the fault, the operation blocking conflicts with the log; and
remove the set translation indicator based upon the fault.

7. The processor of claim 1 , further comprising a second processor core including circuitry to:
determine a miss in a second cache, the second cache including one or more translation indicators from the physical map, the miss for a second translation indicator for a second memory location;
determine whether any log entries exist with information about a received fault from an attempt to store to the second memory location;
invalidate, based on a determination that such log entries exist, invalidate transactions associated with the log entries; and
populate the second cache with an entry from the physical map for the second translation indicator.

8. A method comprising, within a processor:
in a first cache, storing one or more translation indicators from a physical map, each translation indicator to indicate whether a corresponding memory location includes translated code to be protected;
executing, by a first one of a plurality of processor cores of the processor, a translated instruction, the translated instruction translated from an instruction stored in a first memory location;
setting a first translation indicator in the first cache corresponding to the first memory location to indicate that the first memory location includes translated code to be protected; and
in the first processor core, requesting senior store buffer drains of one or more other ones of the plurality of processor cores based upon the execution of the translated instruction, the senior store buffers including store operations that have been dispatched, executed, or retired, but that have not been committed.

9. The method of claim 8 , further comprising:
waiting for an acknowledgment of the request for senior store buffer drains; and
writing results of the translation to a second memory location based upon the acknowledgment.

10. The method of claim 8 , further comprising:
comparing bytes of the first memory location when the translated execution was executed with bytes of the first memory location after the request for senior store buffer drains; and
writing contents of the translation to a second memory location based upon the comparison of the bytes.

11. The method of claim 8 , further comprising allowing incoherence between the first cache of the first processing core and a second cache of a second processing core with respect to whether the first memory location includes translated code to be protected.

12. The method of claim 8 , further comprising:
setting a second translation indicator, the second translation indicator to indicate whether a second memory location includes translated code to be protected; and
in the first processing core, invalidating the second translation indicator in other caches of the processor based upon setting the second translation indicator.

13. The method of claim 8 , further comprising:
receiving a fault from an attempt to store to a memory location with a set translation indicator;
storing information about the attempt to a log based upon the fault;
causing an operation for an associated portion of the physical map for the second memory location based upon the fault, the operation blocking conflicts with the log; and
removing the set translation indicator based upon the fault.

14. A system comprising:
a first one of a plurality of processor cores, including:
a first cache including circuitry to store one or more translation indicators from a physical map, each translation indicator to indicate whether a corresponding memory location includes translated code to be protected; and

circuitry to:
execute a translated instruction, the translated instruction translated from an instruction stored in a first memory location;
set a first translation indicator in the first cache corresponding to the first memory location to indicate that the first memory location includes translated code to be protected; and
request senior store buffer drains of one or more other ones of the plurality of processor cores of the system based upon the execution of the translated instruction, the senior store buffers including store operations that have been dispatched, executed, or retired, but that have not been committed.

15. The system of claim 14 , wherein the first processor core further includes circuitry to:
wait for an acknowledgment of the request for senior store buffer drains; and
write results of the translation to a second memory location based upon the acknowledgment.

16. The system of claim 14 , wherein the first processor core further includes circuitry to:
compare bytes of the first memory location when the translated execution was executed with bytes of the first memory location after the request for senior store bu

Assignees

• Kelm John H
• Keppel David P
• Mackintosh David N
• Intel Corp

Inventors

• Kelm John H
• Keppel David P
• Mackintosh David N

Classifications

• G06F9/30174 Primary

  for non-native instruction set, e.g. Javabyte, legacy code · CPC title

• G06F9/4552 Primary

  Involving translation to a different instruction set architecture, e.g. just-in-time translation in a JVM · CPC title

• G06F12/0875

  with dedicated cache, e.g. instruction or stack · CPC title

• G06F2212/452

  Instruction code · CPC title