Memory device, memory system, and control method performed by the memory system

Patent metadata

Field	Value
Publication number	US-9652180-B2
Application number	US-201414163519-A
Country	US
Kind code	B2
Filing date	Jan 24, 2014
Priority date	Jan 28, 2013
Publication date	May 16, 2017
Grant date	May 16, 2017

Abstract

Provided are a memory device, a memory system, and a control method performed by the memory system. The control method includes operations of generating, by a first function block of the memory system, a main request comprising a first sub-request for a first operation that is requested by an external source and a second sub-request for a second operation that is dependent upon a processing result of the first operation; processing, by a second function block of the memory system, the first sub-request or the second sub-request; and when a processing result of the first sub-request performed by the second function block is a fail, transmitting, by a third function block of the memory system, abortion information to the first function block in response to the main request, regardless of processing the second sub-request.

First claim

What is claimed is:

1. A control method performed by a non-volatile memory system comprising a memory controller and memory device, the control method comprising:
receiving an operation request from an external source by a firmware unit of the memory controller;
in response to receiving the operation request, generating, by the firmware unit, a main request comprising a first sub-request and a second sub-request; wherein the first sub-request is for a first operation of the main request, and the second sub-request is for a second operation of the main request that is dependent upon a processing result of the first operation;
transmitting the first and second sub-requests from the firmware unit to a memory management unit of the memory controller;
in response to receiving the first and second sub-requests, controlling, by the memory management unit, the memory device to initiate the first and second operations, wherein the memory management unit initiates the second operation without waiting for an indication from the memory device that the first operation is complete;
receiving a processing result of the first operation by the memory management unit from the memory device; and
in response to receiving the processing result and determining the processing result indicates the status of the first sub-request is a fail, transmitting, by the memory management unit, abortion information to the firmware unit, wherein the transmitting of the abortion information is performed even if processing of the second sub-request has not completed.

2. The control method of claim 1 , wherein the firmware unit includes commands and data to perform machine code processing that is used by the memory system to process the operation request from the external source.

3. The control method of claim 1 , wherein, in response to the operation request containing a program command, the first sub-request includes a backup program command for a least significant bit (LSB) page of the memory device, the LSB page and a most significant bit (MSB) page of the memory device form a pair, and the second sub-request includes a command to program the MSB page to a word line of the memory device to which the LSB page was programmed.

4. The control method of claim 3 , further comprising:
processing the first sub-request; and
processing the second sub-request,
wherein the processing of the first sub-request comprises:
initiating programming of the LSB page by the memory management unit, and

wherein the processing of the second sub-request comprises:
initiating programming of the MSB page by the memory management unit, even if the programming of the LSB page is not complete.

5. The control method of claim 1 , wherein, in response to the operation request containing a program command for a first memory block of the memory device, the first sub-request includes an erase command for the first memory block, and the second sub-request includes a program command for a first page of the first memory block.

6. The control method of claim 5 , further comprising:
processing the first sub-request; and
processing the second sub-request,
wherein the processing of the first sub-request comprises:
initiating erasing of the first memory block by the memory management unit; and

the processing of the second sub-request comprises:
initiating programming of the first page by the memory management unit, without waiting for an indication that the erasing of the first memory block is complete.

7. The control method of claim 1 , wherein in response to the operation request containing a program command for programming metadata in the memory device, the first sub-request includes a program command for header data of the metadata, and the second sub-request includes a program command for content data of the metadata.

8. The control method of claim 7 , further comprising:
processing the first sub-request; and
processing the second sub-request,
wherein the processing of the first sub-request comprises:
initiating programming of the header data by the memory management unit; and
the processing of the second sub-request comprises:
initiating programming the content data by the memory management unit, even if the programming of the header data is not complete.

9. The control method of claim 1 , wherein, in response to the operation request containing a program command for programming metadata in the memory device, the first sub-request includes a program command for a first part of the metadata, and the second sub-request includes a program command for a second part of the metadata.

10. The control method of claim 9 , further comprising:
processing the first sub-request; and
processing the second sub-request,
wherein the processing of the first sub-request comprises: initiating programming of the first part of the metadata by the memory management unit; and
the processing of the second sub-request comprises:
programming the second part of the metadata by the memory management unit, even if the programming of the first part of the metadata is not complete.

11. The control method of claim 1 , further comprising:
sequentially processing the first sub-request and the second sub-request.

12. The control method of claim 1 , wherein the memory device includes a command queue, and the control method further comprises: enqueuing the first sub-request and the second sub-request in the command queue; and setting the first sub-request and the second sub-request that are enqueued in the command queue as a dependency group.

13. The control method of claim 12 , wherein the transmitting abortion information to the firmware unit comprises: determining whether the processing result of the first sub-request has failed; in response to determining the processing result of the first sub-request has failed, referring to the dependency group, and checking whether the second sub-request is included in the dependency group; and outputting the abortion information with respect to the main request, when the checking indicates the second sub-request is included in the dependency group.

14. The control method of claim 1 , wherein, in response to receiving the abortion information, error processing is not performed by firmware unit with respect to the first sub-request or the second sub-request.

15. The control method of claim 1 , further comprising: retransmitting the main request in response to the abortion information, by the firmware unit.

16. The control method of claim 1 , wherein the main request further includes a third sub-request that requires an operation that is dependent upon a processing result of at least one of the first sub-request and the second sub-request, and the transmitting abortion information to the firmware unit includes transmitting the abortion information to the firmware unit in response to the main request without processing either of the second sub-request and the third sub-request, when the processing result of the first sub-request is a fail.

17. An input and output processing method performed by a NAND flash memory system including a memory controller and a NAND flash device, the input and output processing method comprising:
receiving an operation request from an external source by a firmware unit included in the memory controller;
in response to receiving the operation request, generating, by the firmware unit, a main request including a first sub-request and a second sub-request; wherein the first sub-request is for a first operation of the main request, and the second sub-request is for a second operati

Assignees

• Park Youn-Won
• Lee Su-Ryun
• Lee Byung-Ki
• Lee Sang-Cheol
• Samsung Electronics Co Ltd

Inventors

• Park Youn-Won
• Lee Su-Ryun
• Lee Byung-Ki
• Lee Sang-Cheol

Classifications

• G11C11/5628 Primary

  Programming or writing circuits; Data input circuits · CPC title

• G06F3/0679 Primary

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G11C16/10

  Programming or data input circuits · CPC title

• G11C16/344

  Arrangements for verifying correct erasure or for detecting overerased cells · CPC title

• G11C7/10 Primary

  Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers · CPC title