Fault detection optimized electronic circuit and method

Patent metadata

Field	Value
Publication number	US-9648727-B2
Application number	US-201514602647-A
Country	US
Kind code	B2
Filing date	Jan 22, 2015
Priority date	Jan 22, 2015
Publication date	May 9, 2017
Grant date	May 9, 2017

Abstract

Fault detection optimized electronic circuit includes a circuit substrate on which components of the electronic circuit are respectively disposed. Each of the components has a component body which includes at least a first and second contacts. A component trace formed of conductive material is disposed on a first exterior surface of each component body facing the substrate. The component trace is electrically insulated from the first and second contact. Each of the components contains a network consisting of at least two capacitors connected in series between the first and second contact. A test point is formed of conductive material disposed on a second exterior surface of each body. The test point is electrically isolated from the first and second contacts and electrically connected to at least the component trace.

First claim

I claim:

1. A fault detection optimized electronic circuit, comprising:
a circuit substrate on which are disposed a plurality of circuit traces formed of conductive material and defining a plurality of attachment sites, each attachment site including at least a first and second pad formed of conductive material and respectively connected to one of the circuit traces;
a plurality of components of the electronic circuit which are respectively disposed at the plurality of attachment sites, each said component comprising a surface mount device (SMD) having a body which includes at least a first and second contact formed of a conductive material disposed on at least a first exterior surface of the SMD's body facing the substrate, wherein said first contact is electrically connected to the first pad, and the second contact is electrically connected to the second pad;
a component trace formed of a conductive material disposed on the first exterior surface so as to be spaced apart from and electrically insulated from the first and second contacts;
each of the plurality of components respectively containing a network consisting of at least two capacitors connected in series between the first and second contacts, each capacitor of the at least two capacitors comprising two parallel capacitive plates disposed internal to the SMD's body, a first one of the two parallel capacitive plates connected to a terminal of the network and a second one of the two parallel capacitive plates directly electrically connected to a capacitive plate of the other capacitor of the at least two capacitors at an intermediary node; and
a test point formed of a conductive material disposed on a second exterior surface of the SMD's body, the test point electrically isolated from the first and second contacts and electrically connected to the component trace and the intermediary node.

2. The fault detection optimized electronic circuit according to claim 1 , wherein the second exterior surface is opposed from the first exterior surface.

3. The fault detection optimized electronic circuit according to claim 1 , wherein the first pad at each attachment site is connected to one of the circuit traces that comprises a primary power bus for said electronic circuit, and the second pad is connected to one of the circuit traces that comprises a ground conductor.

4. The fault detection optimized electronic circuit according to claim 1 , wherein the circuit substrate includes a second plurality of attachment sites at which are respectively disposed a second plurality of components, including electronic components other than capacitors.

5. The fault detection optimized electronic circuit according to claim 1 , wherein the component trace extends across the body of the component.

6. The fault detection optimized electronic circuit according to claim 5 , wherein the component trace extends in a direction which is transverse to an axial direction of the component which extends between the first and second contacts.

7. A fault detection optimized electronic circuit, comprising:
a circuit substrate on which are disposed a plurality of circuit traces formed of conductive material and defining a plurality of attachment sites, each attachment site including at least a first and second pad formed of conductive material and respectively connected to one of the circuit traces;
a plurality of components of the electronic circuit which are respectively disposed at the plurality of attachment sites, each said component comprising a surface mount device (SMD) having a body which includes at least a first and second contact formed of conductive material, wherein said first contact is electrically connected to the first pad, and the second contact is electrically connected to the second pad;
a component trace formed of conductive material disposed on a first exterior surface of each said body facing the substrate, the component trace electrically insulated from the first and second contact;
each of the plurality of components respectively containing a network consisting of at least two capacitors connected in series between the first and second contact; and
a test point formed of conductive material disposed on a second exterior surface of each said body, the test point electrically isolated from the first and second contacts and electrically connected to at least the component trace;
wherein the component trace is electrically isolated from all of the circuit traces disposed on said circuit substrate when the electronic circuit is free of any fault.

8. A method for fault detection in an electronic circuit, comprising:
providing a plurality of surface mount device (SMD) components, each said SMD component including a body in which first and second capacitors are internally disposed so as to be connected in series between first and second electrical contacts of the SMD component, each capacitor of the first and second capacitors comprising two parallel capacitive plates, a first one of the two parallel capacitive plates connected to a terminal and a second one of the two parallel plates directly electrically connected to a capacitive plate of the other capacitor of the first and second capacitors at an intermediary node, the first and second electrical contacts formed of a conductive material disposed on at least one exterior surface of the SMD component's body;
providing on the at least one exterior surface of each of said SMD components a component trace formed of a conductive material and electrically insulated from the first and second electrical contacts;
providing a test point formed of conductive material on the at least one exterior surface of each of the SMD components electrically connected to the component trace and the intermediary node;
providing a printed wiring board (PWB) substrate with a plurality of circuit traces formed of conductive material disposed on a surface thereof to define a plurality of attachment sites, each including at least first and second conductive pads;
forming the electronic circuit by positioning one of the SMD components at each of the plurality of attachment sites and performing soldering operations at each attachment site to electrically connect at least the first and second electrical contacts to the first and second conductive pads; and
testing the electronic circuit to determine at least one fault by measuring an impedance or a resistance as between the test point and at least one of the electrical contacts.

9. The method according to claim 8 , selecting the second exterior surface to be opposed from the first exterior surface.

10. The method according to claim 8 , further comprising electrically connecting the first pad at each attachment site to one of the circuit traces that comprises a primary power bus for said electronic circuit, and electrically connecting the second pad to one of the circuit traces that comprises a ground conductor.

11. The method according to claim 8 , further comprising including a second plurality of attachment sites on said PWB substrate at which are disposed respectively a second plurality of SMD components, including electronic components other than capacitors.

12. The method according to claim 9 , further comprising
determining whether the soldering operation has created an electrical short circuit connection directly between the first and second pads at any of the attachment sites; and
identifying one or more of the plurality of attachment sites where the short circuit has occurred by measuring an impedance or resistance as between the test point on an SMD component and at least one of the first and second contact of the SMD component on which the test point is

Assignees

• Harris Corp

Inventors

• Sitzman Justin

Classifications

• H05K2203/162

  Testing a finished product, e.g. heat cycle testing of solder joints · CPC title

• H05K3/3442

  having edge contacts, e.g. leadless chip capacitors, chip carriers · CPC title

• H01G4/40

  Structural combinations of fixed capacitors with other electric elements, the structure mainly consisting of a capacitor, e.g. RC combinations · CPC title

• G01R31/2884

  using dedicated test connectors, test elements or test circuits on the IC under test (G01R31/2855 takes precedence) · CPC title

• H05K2201/10015

  Non-printed capacitor · CPC title