Process of fabricating printed circuit board

Patent metadata

Field	Value
Publication number	US-9648723-B2
Application number	US-201514855635-A
Country	US
Kind code	B2
Filing date	Sep 16, 2015
Priority date	Sep 16, 2015
Publication date	May 9, 2017
Grant date	May 9, 2017

Abstract

A circuit apparatuses include at least one circuit feature formed from patterning a conductive sheet. The conductive sheet includes an irregular surface and a planarized surface. Conductive sheet roughness is minimized in first regions of the circuit apparatus and is maintained in second regions of the circuit apparatus. Selectively planarizing portions of the conductive sheet allows for the utilization of lower cost rougher conductive sheets. The planarized surface allows for increased signal integrity and reduced insertion loss and the irregular surface allows for increased adhesion and enhancing reliability of the circuit apparatus.

First claim

What is claimed is:

1. A process of fabricating a printed circuit board comprising:
attaching a conductive sheet to a first insulator, the conductive sheet comprising an irregular surface opposed to the first insulator;
forming a mask upon a protected portion of the irregular surface;
planarizing an unprotected portion of the irregular surface uncovered by the mask, and;
subsequent to planarizing the unprotected portion, patterning the conductive sheet into at least one circuit feature, the patterned conductive sheet comprising a maintained irregular surface and a planarized surface.

2. The process of claim 1 , wherein planarizing the unprotected portion of the irregular surface further comprises:
electropolishing the unprotected portion of the irregular surface.

3. The process of claim 1 , wherein patterning the conductive sheet into at least one circuit feature further comprises:
subtractive etching a first segment of the conductive sheet, and;
maintaining a second segment to form the at least one circuit feature.

4. The process of claim 1 , wherein patterning the conductive sheet into at least one circuit feature further comprises:
forming a circuit trace comprising the planarized surface, and;
forming a power plane comprising the maintained irregular surface.

5. The process of claim 1 , wherein patterning the conductive sheet into at least one circuit feature further comprises:
forming a high speed signal circuit trace comprising the planarized surface, and;
forming a low speed signal circuit trace comprising the maintained irregular surface.

6. The process of claim 1 , wherein patterning the conductive sheet further comprises:
removing segments of the patterned conductive sheet exposing the underlying first insulator.

7. The process of claim 6 , further comprising:
bonding a second insulator to the patterned conductive sheet and the exposed first insulator.

8. The process of claim 7 , wherein the maintained irregular surface increases bonding between the patterned conductive sheet and the second insulator and wherein the planarized surface reduces insertion loss within the circuit apparatus.

Assignees

• IBM

Inventors

• Carlson Brian L
• Dangler John R
• Krabbenhoft Roger S
• Splittstoesser Kevin A

Classifications

• H05K3/382

  by special treatment of the metal · CPC title

• Y10T29/49156

  with selective destruction of conductive paths · CPC title

• H05K1/0393

  Flexible materials (H05K1/038 takes precedence; specific organic compositions are classified in H05K1/0313 and subgroups) · CPC title

• H05K3/46

  Manufacturing multilayer circuits · CPC title

• H05K2201/0355

  Metal foils · CPC title