Imaging systems and methods for mitigating pixel data quantization error

Patent metadata

Field	Value
Publication number	US-9648265-B2
Application number	US-201414264984-A
Country	US
Kind code	B2
Filing date	Apr 29, 2014
Priority date	Apr 29, 2014
Publication date	May 9, 2017
Grant date	May 9, 2017

Abstract

An image sensor may have an array of pixels and readout circuitry. The array may include image pixels that generate signals in response to image light and reference pixels that generate signals in response to electrical noise. The readout circuitry may obtain first pixel values from the image pixels and may obtain second pixel values from the reference pixels. The readout circuitry may generate an extended precision pixel value based on the second pixel values that have an extended bit width relative to the each of the second pixel values. The readout circuitry may generate multiple dithered correction values by adding randomized sequences of least significant bits to the extended precision pixel value. The readout circuitry may mitigate visible quantization error and noise such as row-correlated and column-correlated noise in the final image by subtracting the dithered correction values from corresponding first pixel values.

First claim

What is claimed is:

1. A method of generating noise-corrected pixel values using an array of image sensor pixels and readout circuitry, wherein the array of image sensor pixels comprises a first group of pixels and a second group of pixels that is different from the first group of pixels, the method comprising:
with the readout circuitry, obtaining a first set of pixel values from the first group of pixels;
with the readout circuitry, obtaining a second set of pixel values from the second group of pixels;
with the readout circuitry, generating a dithered correction value based on the second set of pixel values, wherein each pixel value in the second set of pixel values has a first bit width, and wherein generating the dithered correction value based on the second set of pixel values comprises performing precision extension operations on the second set of pixel values to generate an extended precision pixel value having a second bit width that is greater than the first bit width; and
with the readout circuitry, subtracting the dithered correction value from the first set of pixel values to generate a noise-corrected pixel value.

2. The method defined in claim 1 , wherein generating the dithered correction value further comprises:
multiplying the extended precision pixel value by a scaling factor to generate a scaled extended precision pixel value.

3. The method defined in claim 2 , wherein generating the dithered correction value further comprises:
randomizing at least one bit of the scaled extended precision pixel value to generate the dithered correction value.

4. The method defined in claim 3 , wherein randomizing the at least one bit of the scaled extended precision pixel value comprises:
generating a pseudo random number; and
adding at least one least significant bit of the pseudo random number to the scaled extended precision pixel value to generate the dithered correction value.

5. The method defined in claim 1 , wherein performing the precision extension operations on the second set of pixel values comprises:
summing at least two of the pixel values in the second set to generate the extended precision pixel value.

6. The method defined in claim 1 , further comprising:
performing precision reduction operations on the noise-corrected pixel values so that the noise-corrected pixel values have the first bit width.

7. The method defined in claim 1 , further comprising:
with the first group of pixels, capturing a first set of analog image signals in response to image light from a scene; and
with the second group of pixels, capturing a second set of analog image signals without generating charge in response to the image light.

8. The method defined in claim 7 , further comprising:
with the readout circuitry, performing analog-to-digital conversion operations on the first set of analog image signals to generate the first set of pixel values; and
with the readout circuitry, performing analog-to-digital conversion operations on the second set of analog image signals to generate the second set of pixel values.

9. A method of generating noise-corrected pixel values using an array of image sensor pixels and readout circuitry, wherein the array of image sensor pixels comprises a first group of pixels and a second group of pixels that is different from the first group of pixels, the method comprising:
with the readout circuitry, obtaining a first set of pixel values from the first group of pixels;
with the readout circuitry, obtaining a second set of pixel values from the second group of pixels;
with the readout circuitry, generating a dithered correction value based on the second set of pixel values;
with the readout circuitry, generating an additional dithered correction value based on the second set of pixel values, wherein the dithered correction value has a first randomized sequence of least significant bits and the additional dithered correction value has a second randomized sequence of least significant bits; and
with the readout circuitry, subtracting the dithered correction value from the first set of pixel values to generate a noise-corrected pixel value.

10. The method defined in claim 9 , further comprising:
with the readout circuitry, subtracting the dithered correction value from a first pixel value in the first set of pixel values to generate the noise-corrected pixel value; and
with the readout circuitry, subtracting the additional dithered correction value from a second pixel value in the first set of pixel values to generate an additional noise-corrected pixel value.

11. A method of mitigating signal noise in an imaging system having pixel value correction circuitry, a plurality of image pixels, and at least one reference pixel, the method comprising:
with the pixel value correction circuitry, obtaining a first pixel value from the plurality of image pixels and a second pixel value from the at least one reference pixel;
with the pixel value correction circuitry, generating a random sequence of binary bits;
with the pixel value correction circuitry, adding at least one bit of the random sequence of binary bits to the second pixel value to generate a pixel correction value, wherein adding the at least one bit of the random sequence of binary bits to the second pixel value to generate the pixel correction value comprises adding at least one least significant bit of the random sequence of binary bits to the second pixel value to generate the pixel correction value; and
with the pixel value correction circuitry, subtracting the pixel correction value from the first pixel value.

12. The method defined in claim 11 , wherein obtaining the second pixel value comprises:
receiving a plurality of digital dark pixel values from the at least one reference pixel, wherein each digital dark pixel value of the plurality of digital dark pixel values has a first bit width; and
summing the plurality of digital dark pixel values to generate an extended precision dark pixel value having a second bit width that is greater than the first bit width.

13. The method defined in claim 12 , wherein obtaining the second pixel value further comprises:
multiplying the extended precision dark pixel value by a scaling factor to generate the second pixel value.

14. The method defined in claim 11 , further comprising:
with the pixel value correction circuitry, obtaining a third pixel value from the plurality of image pixels;
with the pixel value correction circuitry, generating an additional random sequence of binary bits that is different from the random sequence of binary bits;
with the pixel value correction circuitry, adding at least one bit of the additional random sequence of binary bits to the second pixel value to generate an additional pixel correction value; and
with the pixel value correction circuitry, subtracting the additional pixel correction value from the third pixel value.

Assignees

• Semiconductor Components Ind Llc

Inventors

• Panicacci Roger
• Beck Jeffery
• Vanhoff Barry

Classifications

• H04N25/63 Primary

  applied to dark current · CPC title

• H04N25/677

  for reducing the column or line fixed pattern noise · CPC title

• H04N25/78

  Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters · CPC title

• H04N5/3658

  Electricity · mapped topic

• H04N5/378 Primary

  Electricity · mapped topic