Non-transparent bridge method and apparatus for configuring high-dimensional PCI-express networks

US9647962B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9647962-B2
Application numberUS-201615236636-A
CountryUS
Kind codeB2
Filing dateAug 15, 2016
Priority dateNov 7, 2014
Publication dateMay 9, 2017
Grant dateMay 9, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

In a high-dimensional PCI-Express (PCIe) network, implementation of alternative paths is accomplished to facilitate flexible topology implementation and network domain scaling while enabling improved communication latency. Different portions of the PCIe tree structure are connected to allow a shorter path for communications by utilizing a bridge circuit configured as an end-point with respect to two switches that are not directly connected in the PCIe tree topology. The bridge circuit performs address translations to allow communications from one switch to be passed via the bridge circuit to the other switch.

First claim

Opening claim text (preview).

The invention claimed is: 1. A PCIe network system comprising: a plurality of switches coupled together to form a PCIe tree topology with a plurality of branches; a plurality of devices coupled to the plurality of branches formed by the switches; and a bridge circuit exposed to a first switch of the plurality of switches by a first range of addresses assigned to the bridge circuit and exposed to a second switch of the plurality of switches by a second range of addresses assigned to the bridge circuit, the bridge circuit being configured to perform address translations to convert a destination address within the first range of addresses to an address of a device coupled to the second switch, and to convert a destination address within the second range of addresses to an address of a device coupled to the first switch. 2. The PCIe network system of claim 1 , wherein the bridge circuit is configured to perform operations of: receiving a first packet from the first switch, wherein the first packet has the destination address within the first range of addresses; replacing the destination address of the first packet with the address of the device coupled to the second switch; forwarding the first packet with the replaced destination address to the second switch; receiving a second packet from the second switch, wherein the second packet has the destination address within the second range of addresses; replacing the destination address of the second packet with the address of the device connected to the first switch; and forwarding the second packet with the replaced destination address to the first switch. 3. The PCIe network system of claim 1 , wherein the bridge circuit comprises: a first network connection connected to the first switch and a second network connection connected to the second switch; a processing circuit; and a memory storing an address translation table that maps the destination address in the first range of addresses to the address of the device coupled to the second switch, and the destination address in the second range of addresses to the address of the device coupled to the first switch. 4. A method performed by a bridge circuit in a PCIe network system to provide a shortened communication path between two portions of a PCIe tree topology of the PCIe network system, comprising: receiving a first packet from a first switch in a first portion of the PCIe tree topology, wherein the first packet has a destination address within a first range of addresses assigned to the bridge circuit with respect to the first switch; replacing the destination address of the first packet with an address of a device coupled to a second switch in a second portion of the PCIe tree topology; forwarding the first packet with the replaced destination address to the second switch; receiving a second packet from the second switch, wherein the second packet has a destination address within a second range of addresses assigned to the bridge circuit with respect to the second switch; replacing the destination address of the second packet with an address of a device coupled to the first switch; and forwarding the second packet with the replaced destination address to the first switch. 5. The method of claim 4 , further comprising: accessing a mapping table stored in the bridge circuit to retrieve the addresses of the devices coupled to the first and second switches based on the destination addresses of the first and second packets.

Assignees

Inventors

Classifications

  • Single bridge functionality, e.g. connection of two networks over a single bridge · CPC title

  • Interconnection of switching modules · CPC title

  • Multipath · CPC title

  • by scheduling the transmission of messages at the communication node · CPC title

  • Discovery or management of network topologies · CPC title

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What does patent US9647962B2 cover?
In a high-dimensional PCI-Express (PCIe) network, implementation of alternative paths is accomplished to facilitate flexible topology implementation and network domain scaling while enabling improved communication latency. Different portions of the PCIe tree structure are connected to allow a shorter path for communications by utilizing a bridge circuit configured as an end-point with respect t…
Who is the assignee on this patent?
Futurewei Technologies Inc
What technology area does this patent fall under?
Primary CPC classification H04L45/48. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue May 09 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).