Power amplification module

Patent metadata

Field	Value
Publication number	US-9647700-B2
Application number	US-201615138239-A
Country	US
Kind code	B2
Filing date	Apr 26, 2016
Priority date	Apr 30, 2015
Publication date	May 9, 2017
Grant date	May 9, 2017

Abstract

A power amplification module includes a first amplification transistor that receives a first signal outputs an amplified second signal from the collector thereof; and a bias circuit that supplies a bias current to the base of the first amplification transistor. The first bias circuit includes a first transistor that is diode connected and is supplied with a bias control current; a second transistor that is diode connected, the collector thereof being connected to the emitter of the first transistor; a third transistor, the base thereof being connected to the base of the first transistor, and the bias current being output from the emitter thereof; a fourth transistor, the collector thereof being connected to the emitter of the third transistor and the base thereof being connected to the base of the second transistor; and a first capacitor between the base and the emitter of the third transistor.

First claim

What is claimed is:

1. A power amplification module comprising:
a first amplification transistor in which a first signal is input to a base of the first amplification transistor and a second signal obtained by amplifying the first signal is output from a collector of the first amplification transistor;
a first resistor; and
a first bias circuit that supplies a first bias current to the base of the first amplification transistor via the first resistor, wherein the first bias circuit comprises:
a first transistor, in which a base or gate of the first transistor is connected to a collector or drain of the first transistor, and a bias control current is supplied to the collector or drain of the first transistor,
a second transistor in which a base and a collector of the second transistor are connected to each other and the collector of the second transistor is connected to an emitter or source of the first transistor,
a third transistor in which a base or gate of the third transistor is connected to the base or gate of the first transistor, an emitter or source of the third transistor is connected to a first end of the first resistor and the first bias current is output from the emitter or source of the third transistor,
a fourth transistor in which a collector of the fourth transistor is connected to the emitter of the third transistor and a base of the fourth transistor is connected to the base of the second transistor, and
a first capacitor that is provided between the base or gate of the third transistor and the emitter or source of the third transistor;

a second amplification transistor in which the second signal is input to a base of the second amplification transistor and a third signal obtained by amplifying the second signal is output from a collector of the second amplification transistor,
a fifth resistor, and
a second bias circuit that supplies a second bias current to the base of the second amplification transistor via the fifth resistor, wherein the second bias circuit comprises:
a fifth transistor in which a base and a collector of the fifth transistor are connected to each other and the bias control current is supplied to the collector of the fifth transistor,
a sixth transistor in which a base and a collector of the sixth transistor are connected to each other and the collector is connected to an emitter of the fifth bipolar transistor, and
a seventh transistor in which a base of the seventh transistor is connected to the base of the fifth transistor, an emitter of the seventh transistor is connected to a first end of the fifth resistor and the second bias current is output from an emitter and the seventh transistor,

the second bias circuit not including a capacitor between the base and the emitter of the seventh transistor.

2. The power amplification module according to claim 1 , wherein an emitter of the fourth transistor is connected to an emitter of the second transistor.

3. The power amplification module according to claim 1 , wherein the first, second, third, and fourth transistors are heterojunction bipolar transistors.

4. The power amplification module according to claim 1 , wherein the first bias circuit further includes a second resistor that is connected in series with the first capacitor between the base and emitter of the third transistor.

5. The power amplification module according to claim 1 , wherein the first bias circuit further includes a third resistor that is provided between the base of the second transistor and the base of the fourth transistor.

6. The power amplification module according to claim 1 , wherein the first bias circuit further includes a second capacitor, in which a first end of the second capacitor is connected to the base of the third transistor and a second end of the second capacitor is connected to the emitter of the fourth transistor.

7. The power amplification module according to claim 1 , wherein the first bias circuit further includes a first field-effect transistor (FET) that controls an electrical connection of the first capacitor between the base and the emitter of the third transistor on the basis of a connection control signal.

8. The power amplification module according to claim 1 , further comprising:
a fourth resistor in which the bias control current is supplied to one end of the fourth resistor and another end of the fourth resistor being connected to the collector of the first transistor.

9. The power amplification module according to claim 1 , wherein
the first and third transistors are field-effect transistors (FET),
the gate of the first transistor and the drain of the first transistor are connected to each other and the bias control current is supplied to the drain of the first transistor, and
the gate of the third transistor is connected to the gate of the first transistor and the source of the third transistor is connected to the first end of the first resistor.

10. The power amplification module according to claim 1 , wherein the fifth, sixth, and seventh transistors are heterojunction bipolar transistors.

11. The power amplification module according to claim 1 , wherein the first bias current is negative along with a change in the first signal.

12. The power amplification module according to claim 1 , wherein an average value of the first bias current does not increase when a level of the first signal increases.

13. The power amplification module according to claim 2 , wherein the first bias circuit further includes a third resistor that is provided between the base of the second transistor and the base of the fourth transistor.

14. The power amplification module according to claim 2 , wherein the first bias circuit further includes a second capacitor, in which a first end of the second capacitor is connected to the base of the third transistor and a second end of the second capacitor is connected to the emitter of the fourth transistor.

15. The power amplification module according to claim 3 , wherein the first bias circuit further includes a second capacitor, in which a first end of the second capacitor is connected to the base of the third transistor and a second end of the second capacitor is connected to the emitter of the fourth transistor.

16. The power amplification module according to claim 2 , further comprising:
a fourth resistor in which the bias control current is supplied to one end of the fourth resistor and another end of the fourth resistor being connected to the collector of the first transistor.

17. The power amplification module according to claim 3 , further comprising:
a fourth resistor in which the bias control current is supplied to one end of the fourth resistor and another end of the fourth resistor being connected to the collector of the first transistor.

Assignees

• Murata Manufacturing Co

Inventors

• Hase Masatoshi

Classifications

• H04B1/04 Primary

  Circuits · CPC title

• H03F2200/411

  the output amplifying stage of an amplifier comprising two power stages · CPC title

• H03F1/0261

  with control of the polarisation voltage or current, e.g. gliding Class A · CPC title

• H03F3/21

  with semiconductor devices only {(H03F3/245 takes precedence)} · CPC title

• H03F1/56

  Modifications of input or output impedances, not otherwise provided for · CPC title