Methods and apparatus for a delta sigma ADC with parallel-connected integrators

Patent metadata

Field	Value
Publication number	US-9647679-B1
Application number	US-201715408890-A
Country	US
Kind code	B1
Filing date	Jan 18, 2017
Priority date	Jun 14, 2016
Publication date	May 9, 2017
Grant date	May 9, 2017

Abstract

Various embodiments of the present technology may comprise a method and device for a delta-sigma ADC. The method and device may comprise receiving an input signal to at least two parallel-connected first-stage integrators and corresponding feedback DACs, and simultaneously integrating the input signal by each of the first-stage integrators. The method and device may further comprise a second stage integrator connected in series with the first-stage integrators, a quantizer, and digital to analog converters, coupled between the output of the quantizer and the inputs of the first-stage integrators.

First claim

The invention claimed is:

1. A delta-sigma modulator with an output terminal, comprising:
at least two first-stage integrators connected in parallel;
a second-stage integrator connected in series with the first-stage integrators, wherein the second-stage integrator is coupled between the at least two first-stage integrators and the output terminal; and
at least two feedback circuits, wherein each feedback circuit is coupled between the output terminal and an input terminal of one of the first-stage integrators.

2. The delta-sigma modulator of claim 1 , wherein:
each feedback circuit comprises a digital-to-analog converter; and
a first digital-to-analog converter is coupled between the output terminal and an input of a first first-stage integrator and a second digital-to-analog converter is coupled between the output terminal and an input of a second first-stage integrator.

3. The delta-sigma modulator of claim 2 , wherein each of the digital-to-analog converters comprises a capacitor having a capacitance value, and wherein the capacitance value of the first digital-to-analog converter is substantially equal to the capacitance value of the second digital-to-analog converter.

4. The delta-sigma modulator of claim 1 , further comprising a summer circuit configured to sum outputs of the at least two first-stage integrators.

5. The delta-sigma modulator of claim 1 , further comprising a combination unit coupled to output terminals of the at least two first-stage integrators and the second-stage integrator, and configured to sum output signals of the at least two first-stage integrators and the second-stage integrator.

6. The delta-sigma modulator of claim 1 , further comprising a quantizer coupled to an output terminal of the second-stage integrator, wherein a quantizer output terminal is coupled to output terminal of the delta-sigma modulator.

7. The delta-sigma modulator of claim 1 , wherein:
each first-stage integrator comprises at least one of each of a capacitor, a switching device, and an operational amplifier; and
the capacitors of the first-stage integrators have capacitance values that are substantially equal to each other, the switching devices of the first-stage integrators are substantially equal in size, and the op-amps of the first-stage integrators have substantially equal topology and size.

8. A method for operating a delta-sigma modulator with an increased signal-to-noise ratio comprising:
receiving an input signal by a first first-stage integrator and a second first-stage integrator, wherein the first and second first-stage integrators are connected in parallel;
simultaneously integrating the input signal by first and second first-stage integrators; and
transmitting a first output signal to a second-stage integrator connected in series with the first and second first-stage integrators.

9. The method of claim 8 , further comprising summing an output of the first first-stage integrator output with an output of the second first-stage integrator.

10. The method of claim 8 , further comprising transmitting a second output signal from an output terminal of the delta-sigma modulator to a first digital-to-analog converter and a second digital-to-analog converter, wherein the first and second digital-to-analog converters are responsive to the second output signal.

11. The method of claim 10 , further comprising transmitting:
an output of the first digital-to-analog converter to the first first-stage integrator; and
an output of the second digital-to-analog converter to the second first-stage integrator.

12. The method of claim 8 , further comprising:
summing outputs of:
the first first-stage integrator, the second first-stage integrator, and the second quantizing a sum of outputs; and

quantizing the sum.

13. A system, comprising:
a micro electro-mechanical device;
a delta-sigma modulator coupled to the micro electro-mechanical device, comprising:
at least first and second first-stage integrators connected in parallel;
a second-stage integrator connected in series with the first-stage integrators;
a first feedback circuit coupled between an output of the delta-sigma modulator and an input of the first first-stage integrator; and
a second feedback circuit coupled between the output of the delta-sigma modulator and an input of the second first-stage integrator; and

a digital circuit coupled to the output of the delta-sigma modulator.

14. The system of claim 13 , wherein:
the first feedback circuit comprises a first digital-to-analog converter;
an input of the first digital-to-analog converter is coupled to the output of the delta-sigma modulator and an output of the first digital-to-analog converter is coupled to the input of the first first-stage integrator.

15. The system of claim 14 , wherein:
the second feedback circuit comprises a second digital-to-analog converter;
an input of the second digital-to-analog converter is coupled to the output of the delta-sigma modulator and an output of the second digital-to-analog converter is coupled to the input of the second first-stage integrator.

16. The system of claim 13 , further comprising a combination unit coupled to output terminals of the first and second first-stage integrators and the second-stage integrator, wherein the combination unit is configured to sum output signals of the first and second first-stage integrators and the second-stage integrator.

17. The system of claim 13 , further comprising a summer circuit coupled to an output terminal of the first first-stage integrator and an output terminal of the second first-stage integrator.

18. The system of claim 13 , further comprising a quantizer coupled to an output terminal of the second-stage integrator, wherein a quantizer output terminal is coupled to output terminal of the delta-sigma modulator.

19. The system of claim 13 , wherein:
each first-stage integrator comprises at least one of each of a capacitor, a switching device, and an operational amplifier; and
the capacitors of the first-stage integrators have capacitance values that are substantially equal to each other, the switching devices of the first-stage integrators are substantially equal in size, and the op-amps of the first-stage integrators have substantially equal topology and size.

20. The system of claim 13 , wherein each of the digital-to-analog converters comprises a capacitor having a capacitance value, and wherein the capacitance value of the first digital-to-analog converter is substantially equal to the capacitance value of the second digital-to-analog converter.

Assignees

• Semiconductor Components Ind Llc

Inventors

• Onishi Akinobu

Classifications

• H04R19/005

  using semiconductor materials · CPC title

• H04R2201/003

  Mems transducers or their use · CPC title

• H03M3/422

  having one quantiser only · CPC title

• H04R3/06

  of electrostatic transducers · CPC title

• H03M3/30

  Delta-sigma modulation · CPC title