Low-power, small-area, high-speed master-slave flip-flop circuits and devices including same

Patent metadata

Field	Value
Publication number	US-9647644-B2
Application number	US-201514613414-A
Country	US
Kind code	B2
Filing date	Feb 4, 2015
Priority date	Dec 8, 2014
Publication date	May 9, 2017
Grant date	May 9, 2017

Abstract

An integrated circuit includes a plurality of positive edge-triggered master-slave flip-flop circuits sharing a clock signal. At least one of the positive edge-triggered master-slave flip-flop circuits includes; an input stage that provides a first output signal generated from an input signal in response to the clock signal and an inverted clock signal, a first inverting circuit that generates the inverted clock signal by delaying the clock signal, a transmission gate that receives a second output signal and generates a final output signal, and a second inverting circuit that receives the first output signal and generates the second output signal from the first output signal. The clock signal is applied to an NMOS transistor of the transmission gate and a PMOS transistor of the input stage, and the inverted clock signal is applied to a PMOS transistor of the transmission gate and an NMOS transistor of the input stage.

First claim

What is claimed is:

1. A system on chip comprising:
at least one functional component including a plurality of positive edge-triggered master-slave flip-flop circuits sharing a clock signal,
wherein at least one of the positive edge-triggered master-slave flip-flop circuits comprises
an input stage configured to receive an input signal, and that includes a p-channel metal oxide semiconductor (PMOS) transistor and a n-channel MOS (NMOS) transistor, and the input stage is configured to provide a first output signal generated from the input signal in response to the clock signal and an inverted clock signal at a first time when the clock signal transitions from low to high;
a first inverting circuit configured to generate the inverted clock signal by delaying the clock signal, wherein the inverted clock signal transitions from high to low at a second time following the first time;
a transmission gate including a PMOS transistor and an NMOS transistor configured to receive a second output signal and generate a final output signal from the second output signal in response to the clock signal and the inverted clock signal; and
a second inverting circuit configured to receive the first output signal and generate the second output signal from the first output signal,
wherein the clock signal is applied to a gate of the NMOS transistor of the transmission gate and a gate of the PMOS transistor of the input stage, and the inverted clock signal is applied to a gate of the PMOS transistor of the transmission gate and a gate of the NMOS transistor of the input stage, and
wherein the input signal comprises a plurality of input bits, and the input stage is configured to logically combine input bits selected from the plurality of input bits in response to the clock signal and the inverted clock signal to generate a logical combination result, invert at least one of the input bits combined in the logical combination result to generate an inverted signal, and provide the inverted signal to the second inverting circuit as the first output signal.

2. The system on chip of claim 1 , wherein before the first time, the input stage is configured to be enabled and the transmission gate is configured to be disabled in response to the clock signal and the inverted clock signal, such that the final output signal has either the same phase or an opposite phase relative to the phase of the input signal.

3. The system on chip of claim 1 , wherein the first inverting circuit is implemented using one of:
a single inverter configured to receive the clock signal and generate the inverted clock signal from the clock signal;
a single NAND gate configured to perform a NAND operation on a control signal and the clock signal to generate the inverted clock signal; and
a single NOR gate configured to perform a NOR operation on a control signal and the clock signal to generate the inverted clock signal, and
the second inverting circuit is implemented using one of
a single inverter configured to receive the first output signal and generate the second output signal from the first output signal;
a single NAND gate configured to perform a NAND operation on another control signal and the first output signal to generate the second output signal; and
a single NOR gate configured to perform a NOR operation on the another control signal and the first output signal to generate the second output signal.

4. A mobile computing device comprising:
an application processor including at least one functional component;
a power management integrated circuit configured to provide an operating voltage to the application processor;
a memory configured to receive data from the application processor; and
a display controlled by the application processor,
wherein the at least one functional component includes a plurality of positive edge-triggered master-slave flip-flop circuits sharing a clock signal, and
one of the plurality of positive edge-triggered master-slave flip-flop circuits comprises
an input stage configured to receive an input signal, and that includes a p-channel metal oxide semiconductor (PMOS) transistor and a n-channel MOS (NMOS) transistor, and the input stage is configured to provide a first output signal generated from the input signal in response to the clock signal and an inverted clock signal at a first time when the clock signal transitions from low to high;
a first inverting circuit configured to generate the inverted clock signal by delaying the clock signal, wherein the inverted clock signal transitions from high to low at a second time following the first time;
a transmission gate including a PMOS transistor and an NMOS transistor configured to receive a second output signal and generate a final output signal from the second output signal in response to the clock signal and the inverted clock signal; and
a second inverting circuit configured to receive the first output signal and generate the second output signal from the first output signal,
wherein the clock signal is applied to a gate of the NMOS transistor of the transmission gate and a gate of the PMOS transistor of the input stage, and the inverted clock signal is applied to a gate of the PMOS transistor of the transmission gate and a gate of the NMOS transistor of the input stage, and
wherein the second inverting circuit comprises a single logic gate configured to set and reset the one of the plurality of positive edge-triggered master-slave flip-flop circuits responsive to a control signal.

5. The mobile computing device of claim 4 , wherein the at least one functional component is one of a central processing unit (CPU), a graphics processing unit (GPU), a core of a multi-core processor, a digital signal processor (DSP), an image signal processor (ISP), a hardware coder/decoder (CODEC), a multimedia processor, and a memory interface.

6. The mobile computing device of claim 4 , wherein the single logic gate comprises a single NOR gate configured to perform a NOR operation on the control signal and the clock signal to generate the inverted clock signal.

7. The integrated circuit of claim 4 , wherein the single logic gate comprises a single NAND gate configured to perform a NAND operation on the control signal and the clock signal to generate the inverted clock signal.

Assignees

• Kim Min Su
• Kim Jong Woo
• Kim Ji Kyum
• Samsung Electronics Co Ltd

Inventors

• Kim Min Su
• Kim Jong Woo
• Kim Ji Kyum

Classifications

• H03K3/0372 Primary

  of the primary-secondary type · CPC title

• H03K3/3562

  of the primary-secondary type · CPC title

• H03K3/356008

  ensuring a predetermined initial state when the supply voltage has been applied; storing the actual state when the supply voltage fails (digital storage cells each combining volatile and non-volatile storage properties G11C14/00) · CPC title

• H03K3/356 Primary

  Bistable circuits · CPC title

• H03K19/0002

  Multistate logic (H03K19/02 takes precedence) · CPC title