Transceiver using technique for improvement of phase noise and switching of phase lock loop (PLL)

Patent metadata

Field	Value
Publication number	US-9647609-B2
Application number	US-201313891474-A
Country	US
Kind code	B2
Filing date	May 10, 2013
Priority date	May 10, 2012
Publication date	May 9, 2017
Grant date	May 9, 2017

Abstract

A transceiver may include a reception (Rx) radio frequency (RF) part configured to process a received signal, a transmission (Tx) RF part configured to process a transmitted signal, and a phase lock loop (PLL) configured to provide a reception frequency to the reception RF part and provide a transmission frequency to the transmission RF part. The PLL may be controlled according to whether the reception RF part or the transmission RF part is on. In addition, a transceiver may include quenching waveform generator (QWGs) to control quenching waveforms of the RF parts corresponding to a plurality of antennas. The quenching waveforms may be generated respectively by VCOs operating at a same frequency. The QWGs may control the VCOs such that the quenching waveforms do not overlap.

First claim

What is claimed is:

1. A transceiver, comprising:
a reception (Rx) radio frequency (RF) part configured to process a received signal;
a transmission (Tx) RF part configured to process a transmitted signal; and
a phase lock loop (PLL) configured to provide a reception frequency to the reception RF part and provide a transmission frequency to the transmission RF part,
wherein the PLL is controlled according to whether the reception RF part or the transmission RF part is on,
wherein the PLL comprises a charge pump that is sequentially controlled to decrease lock time of the PLL and to subsequently decrease phase noise when the PLL is turned off.

2. The transceiver of claim 1 , wherein the PLL comprises:
a reception voltage controlled oscillator (VCO Rx) configured to generate the reception frequency; and
a transmission VCO (VCO Tx) configured to generate the transmission frequency.

3. The transceiver of claim 2 , wherein the PLL comprises a single common control circuit connected to the VCO Rx and the VCO Tx.

4. The transceiver of claim 3 , wherein the PLL is configured to turn on the single common control circuit according to whether the Rx RF part or the Tx RF part is turned on.

5. The transceiver of claim 3 , wherein the PLL comprises switches connected to the VCO Rx and the VCO Tx, and the single common control circuit is connected to the VCO Rx and the VCO Tx through the switches which are switched according to whether the Rx RF part or the Tx RF part is turned on.

6. The transceiver of claim 3 , wherein the single common control circuit comprises:
a loop filter (LF) configured to vary a control voltage according to a predetermined amount of charges for the VCO Rx or the VCO Tx,
wherein the charge pump is further configured to pump a predetermined amount of charges corresponding to a pulse width detected by a phase frequency detector (PFD).

7. The transceiver of claim 6 , wherein the PLL further comprises:
a mismatch compensation device configured to independently control a magnitude of a source current applied to the main CP and a magnitude of a sink current applied to the main CP to compensate for a current mismatch generated in the main CP.

8. The transceiver of claim 7 , wherein the mismatch compensation device comprises:
a first tuning device configured to control a sink current of an auxiliary CP according to a result detected from a sensing capacitor and perform discrete tuning with respect to the current mismatch generated in the main CP by; and
a second tuning device comprising a mismatch current mirror configured to compensate for the current mismatch based on a result of the discrete tuning.

9. The transceiver of claim 8 , wherein the first tuning device comprises:
a CP controller configured to detect a voltage generated by the sensing capacitor and to control the sink current of the auxiliary CP according to the detected voltage; and
a clock generator configured to provide the CP controller with an external clock supplied from outside of the PLL.

10. The transceiver of claim 8 , wherein the second tuning device further comprises:
a replica CP configured to provide the result of the discrete tuning; and
a comparator configured to compare voltages of opposite poles of the sensing capacitor and generate a result;
wherein the mismatch current mirror is further configured to compensate for the current mismatch based on the result of the comparator.

11. The transceiver of claim 6 , wherein the PLL is configured to control a lock time with respect to the reception frequency or the transmission frequency by controlling a bandwidth of the main CP.

12. The transceiver of claim 11 , wherein the PLL is configured to accelerate the lock time by increasing the bandwidth of the main CP and to control phase noise caused when the PLL is turned off by reducing the bandwidth of the main CP.

13. The transceiver of claim 2 , wherein the VCO Rx or the VCO Tx comprises a class-C type VCO including an inductor capacitor (LC) tank.

14. The transceiver of claim 2 , wherein the PLL comprises a leakage compensation device configured to compensate for a voltage leaking from the VCO Rx or the VCO Tx when the PLL is turned off.

15. The transceiver of claim 14 , wherein the leakage compensation device is configured to compensate for the leaking voltage using:
a locked control voltage at the time the transmission frequency locks or the time the reception frequency lock; and
a control voltage that is varied when the Rx RF part or the Tx RF part is turned off.

16. The transceiver of claim 15 , wherein the leakage compensation device comprises:
an analog to digital converter (ADC) configured to generate a digital signal based on a difference between the locked control voltage and the varied control voltage; and
a leakage current control device configured to generate a control signal, based on the digital signal, to control a leakage compensation CP configured to compensate for leaking charges.

17. The transceiver of claim 16 , wherein the leakage compensation device is further configured to control a control voltage of the VCO Rx or the VCO Tx by controlling a resolution of the ADC.

18. The transceiver of claim 15 , wherein the leakage compensation device comprises:
a comparator configured to compare a difference between the locked control voltage and the varied control voltage; and
a leakage current control device configured to generate a control signal, based on a comparison result, to control a leakage compensation CP to compensate for leaking charges.

19. The transceiver of claim 1 , wherein the PLL controls a reception lock time for a reception frequency and a transmission lock time for a transmission frequency by controlling a bandwidth of the charge pump.

20. A transceiver, comprising:
a reception (Rx) radio frequency (RF) part configured to process a received signal,
a transmission (Tx) RF part configured to process a transmitted signal, and
a phase lock loop (PLL) configured to provide a reception frequency to the reception RF part and provide a transmission frequency to the transmission RF part,
wherein the PLL is controlled according to whether the reception RF part or the transmission RF part is on, and
wherein the PLL comprises:
a reception voltage controlled oscillator (VCO Rx) configured to generate the reception frequency;
a transmission VCO (VCO Tx) configured to generate the transmission frequency, and
a single common control circuit connected to the VCO Rx and the VCO Tx, wherein the single common control circuit comprises:
a main charge pump (CP) configured to pump a predetermined amount of charges corresponding to a pulse width detected by a phase frequency detector (PFD); and
a loop filter (LF) configured to vary a control voltage according to the predetermined amount of charges for the VCO Rx or the VCO Tx.

21. The transceiver of claim 20 , wherein the PLL further comprises:
a mismatch compensation device configured to independently control a magnitude of a source current applied to the main CP and a magnitude of a sink current applied to the main CP to compensate for a current mismatch generated in the main CP.

22. The transceiver of claim 21 , wherein the mismatch compensation device comprises:
a first tuning device configured to control a sink current of an auxiliary CP according to a result detected from a sensing capacitor and perform discrete tuning with respect to the current mismatch generated in the main CP by; an

Assignees

• Samsung Electronics Co Ltd
• Sungkyunkwan Univ Found For Corp Collaboration

Inventors

• Lee Jaesup
• Kim Hong Jin
• Park Hyung Gu
• Lee Kang Yoon

Classifications

• H03C3/0916

  with frequency divider or counter in the loop · CPC title

• H04L2027/0022

  using the carrier of the associated receiver of a transceiver · CPC title

• H03L7/0898

  the source or sink current values being variable (H03L7/0896 takes precedence) · CPC title

• H03B5/1215 Primary

  the current source or degeneration circuit being in common to both transistors of the pair, e.g. a cross-coupled long-tailed pair · CPC title

• H03L7/1072

  by changing characteristics of the charge pump, e.g. changing the gain · CPC title