Charge pump based on a clock generator integrated chip

Patent metadata

Field	Value
Publication number	US-9647539-B1
Application number	US-201615180849-A
Country	US
Kind code	B1
Filing date	Jun 13, 2016
Priority date	Dec 9, 2015
Publication date	May 9, 2017
Grant date	May 9, 2017

Abstract

A charge pump includes chip, package substrate and circuit board. Chip includes transistor set including at least four transistors connected to first input end of input terminal set and two rows of odd number and even number second input ends of input terminal set. Except first transistor, the other transistors are arranged in two rows subject to odd number and even number and respectively electrically coupled to the two rows of at least three second input ends by traces. At least three second external pins of package substrate and at least three capacitors of circuit board are respectively arranged in two rows subject to odd number and even number, enabling first circuit with connected odd number second external pins and second circuit with connected even number second external pin to be kept apart without intersection. Traces in chip are arranged in staggered manner, reducing parasitic capacitance.

First claim

What the invention claimed is:

1. A charge pump for use in a touch panel, comprising a chip, a package substrate and a circuit board, wherein:
said chip comprises a clock generator, a first clock terminal and a second clock terminal respectively and electrically coupled to said clock generator, a transistor set, an input terminal set comprising a first input end and at least three second input ends, a load circuit and an output terminal, said transistor set comprising a first transistor and at least three second transistors respectively and electrically coupled to said first input end and said at least three second input ends of said input terminal set, said at least three second input ends being arranged into two rows subject to odd number and even number, each said second input end of odd number being disposed adjacent to said first clock terminal, each said second input end of even number being disposed remote from said first clock terminal, said first transistor of said transistor set being electrically coupled to said first input end by a straightly extended trace, said at least three second transistors being arranged into rows subject to odd number and even number and respectively electrically coupled to said at least three second input ends by respective traces, each two adjacent said second transistors being electrically coupled to one another with the last said second transistor electrically coupled to said load circuit, said load circuit being electrically coupled to a touch panel;
said package substrate carries said package substrate, comprising a first clock pin, a second clock pin and an external pin set, said first clock pin and said second clock pin being respectively electrically coupled to said first clock terminal and said second clock terminal of said chip, said external pin set comprising a first external pin located at one side and at least three second external pins located at an opposite side, said at least three second external pins being arranged in two rows subject to odd number and even number, said first external pin being electrically coupled to said first input end of said chip, said at least three second external pins being respectively electrically coupled to said at least three second input ends of said chip;
said circuit board carries said package substrate, comprising a capacitor set, a first circuit, a second circuit and a logic high/low power supply, said capacitor set comprising at least three capacitors arranged in two rows subject to odd number and even number, said logic high/low power supply being electrically coupled to said first external pin of said package substrate, said first circuit and said second circuit being adapted for electrically coupling the two rows of said at least three said second external pins to the two rows of said at least three capacitors, the odd number said capacitor being electrically coupled to said first clock pin of said package substrate by said first circuit, the even number said capacitors being electrically coupled to said second clock pin of said package substrate by said second circuit.

2. The charge pump as claimed in claim 1 , wherein said clock generator of said chip is disposed at one side relative to said transistor set so that said first clock pin of said package substrate is disposed adjacent to the odd number said second external pins of said package substrate with said second clock pin and the even number said second external pins respectively disposed adjacent two opposite lateral sides thereof, said second circuit of said circuit board being disposed at an outer side relative to said first circuit in a non-staggered manner.

3. The charge pump as claimed in claim 1 , wherein said clock generator of said chip is located on the center of a lower side relative to said transistor set so that said first clock pin of said package substrate is disposed adjacent to the odd number said second external pins and said second clock pin is disposed adjacent to the even number said second external pin with said first circuit and said second circuit of said circuit board respectively disposed at two opposite sides in a non-staggered manner.

4. The charge pump as claimed in claim 1 , wherein the drains of said transistors are respectively electrically connected to the respective gates of the respective said transistors; the connection points between the drains and gates of said transistors are respectively and electrically connected to said first input end and said at least three second input ends of said input terminal set; the sources of said transistors are respectively electrically connecting to the connection points between the drains and gates of the adjacent said transistors with the source of the last said transistor electrically connected to said load circuit.

5. The charge pump as claimed in claim 1 , wherein said clock generator of said chip is configured to provide a pulse signal to said first clock terminal and a negative pulse signal to said second clock terminal.

6. The charge pump as claimed in claim 1 , wherein said clock generator of said chip is configured to provide a negative pulse signal to said first clock terminal and a pulse signal to said second clock terminal.

7. The charge pump as claimed in claim 1 , wherein the last said transistor of said transistor set of said chip is electrically coupled to said output terminal; said package substrate further comprises a transmission pin electrically coupled to said output terminal; said circuit board further comprises a storage circuit electrically coupled to said transmission pin, said storage circuit comprising an external capacitor, external capacitor having one end thereof electrically coupled to said transmission pin and an opposite end thereof grounded.

Assignees

• Egalax_Empia Tech Inc

Inventors

• Lin Po-Chuan

Classifications

• G06F3/041

  Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means · CPC title

• H01L27/088

  Electricity · mapped topic

• H02M3/07 Primary

  using capacitors charged and discharged alternately by semiconductor devices with control electrode {, e.g. charge pumps} · CPC title

• H02M3/075

  including a plurality of stages and two sets of clock signals, one set for the odd and one set for the even numbered stages · CPC title

• G06F3/0416 Primary

  Control or interface arrangements specially adapted for digitisers · CPC title